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From: "Pali Rohár" <pali@kernel.org>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de,
	devicetree@vger.kernel.org, matthias.bgg@gmail.com,
	john@phrozen.org, bhelgaas@google.com, robh+dt@kernel.org,
	linux-staging@lists.linux.dev, gregkh@linuxfoundation.org,
	neil@brown.name, ilya.lipnitskiy@gmail.com,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH 2/4] MIPS: pci: Add driver for MT7621 PCIe controller
Date: Mon, 31 May 2021 15:14:31 +0200	[thread overview]
Message-ID: <20210531131431.bzsvmefqdyawmeo2@pali> (raw)
In-Reply-To: <20210515124055.22225-3-sergio.paracuellos@gmail.com>

On Saturday 15 May 2021 14:40:53 Sergio Paracuellos wrote:
> This patch adds a driver for the PCIe controller of MT7621 SoC.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  arch/mips/pci/Makefile     |   1 +
>  arch/mips/pci/pci-mt7621.c | 624 +++++++++++++++++++++++++++++++++++++
>  arch/mips/ralink/Kconfig   |   9 +-
>  3 files changed, 633 insertions(+), 1 deletion(-)
>  create mode 100644 arch/mips/pci/pci-mt7621.c
> 
> diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
> index f3eecc065e5c..178c550739c4 100644
> --- a/arch/mips/pci/Makefile
> +++ b/arch/mips/pci/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_PCI_AR2315)	+= pci-ar2315.o
>  obj-$(CONFIG_SOC_AR71XX)	+= pci-ar71xx.o
>  obj-$(CONFIG_PCI_AR724X)	+= pci-ar724x.o
>  obj-$(CONFIG_PCI_XTALK_BRIDGE)	+= pci-xtalk-bridge.o
> +obj-$(CONFIG_PCI_MT7621)	+= pci-mt7621.o
>  #
>  # These are still pretty much in the old state, watch, go blind.
>  #
> diff --git a/arch/mips/pci/pci-mt7621.c b/arch/mips/pci/pci-mt7621.c
> new file mode 100644
> index 000000000000..fe1945819d25
> --- /dev/null
> +++ b/arch/mips/pci/pci-mt7621.c
...
> +static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
> +{
> +	struct device *dev = pcie->dev;
> +	struct mt7621_pcie_port *port;
> +	u8 num_slots_enabled = 0;
> +	u32 slot;
> +	u32 val;
> +	int err;
> +
> +	/* Setup MEMWIN and IOWIN */
> +	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
> +	pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
> +
> +	list_for_each_entry(port, &pcie->ports, list) {
> +		if (port->enabled) {
> +			err = clk_prepare_enable(port->clk);
> +			if (err) {
> +				dev_err(dev, "enabling clk pcie%d\n", slot);
> +				return err;
> +			}
> +
> +			mt7621_pcie_enable_port(port);
> +			dev_info(dev, "PCIE%d enabled\n", port->slot);
> +			num_slots_enabled++;
> +		}
> +	}
> +
> +	for (slot = 0; slot < num_slots_enabled; slot++) {
> +		val = read_config(pcie, slot, PCI_COMMAND);
> +		val |= PCI_COMMAND_MASTER;
> +		write_config(pcie, slot, PCI_COMMAND, val);

Hello! Is this part of code correct? Because it looks strange if PCIe
controller driver automatically enables PCI bus mastering, prior device
driver initialize itself.

Moreover kernel has already function pci_set_master() for this purpose
which is used by device drivers.

So I think this code can confuse some device drivers...

> +		/* configure RC FTS number to 250 when it leaves L0s */
> +		val = read_config(pcie, slot, PCIE_FTS_NUM);
> +		val &= ~PCIE_FTS_NUM_MASK;
> +		val |= PCIE_FTS_NUM_L0(0x50);
> +		write_config(pcie, slot, PCIE_FTS_NUM, val);
> +	}
> +
> +	return 0;
> +}

  reply	other threads:[~2021-05-31 13:14 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-15 12:40 [PATCH 0/4] MIPS: ralink: pci: driver for Pcie controller in MT7621 SoCs Sergio Paracuellos
2021-05-15 12:40 ` [PATCH 1/4] dt-bindings: mt7621-pci: PCIe binding documentation for " Sergio Paracuellos
2021-05-31 11:45   ` Sergio Paracuellos
2021-06-04 19:35   ` Rob Herring
2021-06-04 21:32     ` Sergio Paracuellos
2021-06-05 15:06       ` Sergio Paracuellos
2021-05-15 12:40 ` [PATCH 2/4] MIPS: pci: Add driver for MT7621 PCIe controller Sergio Paracuellos
2021-05-31 13:14   ` Pali Rohár [this message]
2021-05-31 13:39     ` Sergio Paracuellos
2021-05-31 13:50       ` Pali Rohár
2021-05-31 14:19         ` Sergio Paracuellos
2021-06-02 12:16           ` Sergio Paracuellos
2021-06-02 12:23             ` Pali Rohár
2021-06-02 12:43               ` Sergio Paracuellos
2021-06-04 16:55                 ` Pali Rohár
2021-06-04 18:44                   ` Sergio Paracuellos
2021-06-04 23:07                     ` Pali Rohár
2021-06-05  5:13                       ` Sergio Paracuellos
2021-06-04 18:49                   ` Rob Herring
2021-06-04 22:58                     ` Pali Rohár
2021-06-05  5:11                       ` Sergio Paracuellos
2021-06-04 19:30   ` Rob Herring
2021-06-04 22:25     ` Sergio Paracuellos
2021-06-07  6:45       ` Sergio Paracuellos
2021-06-04 19:49   ` Bjorn Helgaas
2021-06-04 21:19     ` Sergio Paracuellos
2021-05-15 12:40 ` [PATCH 3/4] staging: mt7621-pci: remove driver from staging Sergio Paracuellos
2021-06-04 13:08   ` Greg KH
2021-05-15 12:40 ` [PATCH 4/4] MAINTAINERS: add myself as maintainer of the MT7621 PCI controller driver Sergio Paracuellos
2021-05-19 20:36 ` [PATCH 0/4] MIPS: ralink: pci: driver for Pcie controller in MT7621 SoCs Bjorn Helgaas
2021-05-19 21:18   ` Sergio Paracuellos
2021-05-21 10:23     ` Thomas Bogendoerfer
2021-05-31 13:18       ` Pali Rohár
2021-06-04 19:43         ` Bjorn Helgaas
2021-06-04 21:15           ` Sergio Paracuellos

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