From: "Pali Rohár" <email@example.com>
To: Bjorn Helgaas <firstname.lastname@example.org>
Cc: "Stefan Chulski" <email@example.com>,
"Bjorn Helgaas" <firstname.lastname@example.org>,
"Thomas Petazzoni" <email@example.com>,
"Marek Behún" <firstname.lastname@example.org>, "Stefan Roese" <email@example.com>,
"Phil Sutter" <firstname.lastname@example.org>, "Mario Six" <email@example.com>,
"Lorenzo Pieralisi" <firstname.lastname@example.org>,
Subject: Re: [EXT] Re: pci mvebu issue (memory controller)
Date: Wed, 2 Jun 2021 23:13:35 +0200 [thread overview]
Message-ID: <20210602211335.oe6r35ctkdtc52ic@pali> (raw)
On Wednesday 02 June 2021 16:01:01 Bjorn Helgaas wrote:
> On Wed, Jun 02, 2021 at 10:39:17PM +0200, Pali Rohár wrote:
> > On Wednesday 02 June 2021 14:14:55 Bjorn Helgaas wrote:
> > > On Wed, Jun 02, 2021 at 01:07:03PM +0200, Pali Rohár wrote:
> > >
> > > > In configuration with *bad* suffix is used U-Boot which does not ignore
> > > > PCIe device Memory controller and configure it when U-Boot initialize.
> > > > In this configuration loaded kernel is unable to initialize wifi cards.
> > > >
> > > > In configuration with *ok* suffix is U-Boot explicitly patched to
> > > > ignores PCIe device Memory controller and loaded kernel can use wifi
> > > > cards without any issue.
> > > >
> > > > In both configurations is used same kernel version. As I wrote in
> > > > previous emails kernel already ignores and hides Memory controller PCIe
> > > > device, so lspci does not see it.
> > > >
> > > > In attachment I'm sending dmesg and lspci outputs from Linux and pci
> > > > output from U-Boot.
> > > >
> > > > What is suspicious for me is that this Memory controller device is at
> > > > the same bus as wifi card. PCIe is "point to point", so at the other end
> > > > of link should be only one device... Therefore I'm not sure if kernel
> > > > can handle such thing like "two PCIe devices" at other end of PCIe link.
> > > >
> > > > Could you look at attached logs if you see something suspicious here? Or
> > > > if you need other logs (either from U-Boot or kernel) please let me
> > > > know.
> > > >
> > > > Note that U-Boot does not see PCIe Bridge as it is emulated only by
> > > > kernel. So U-Boot enumerates buses from zero and kernel from one (as
> > > > kernel's bus zero is for emulated PCIe Bridges).
> > >
> > > I've lost track of what the problem is or what patch we're evaluating.
> > With bad uboot (which enumerates and initialize all PCIe devices,
> > including that memory controller), linux kernel is unable to use PCIe
> > devices. E.g. ath10k driver fails to start. If bad uboot has disabled
> > PCIe device initialization then kernel has no problems.
> > > Here's what I see from dmesg/lspci/uboot:
> > >
> > > # dmesg (both bad/ok) and lspci:
> > > 00:01.0 [11ab:6820] Root Port to [bus 01]
> > > 00:02.0 [11ab:6820] Root Port to [bus 02]
> > > 00:03.0 [11ab:6820] Root Port to [bus 03]
> > > 01:00.0 [168c:002e] Atheros AR9287 NIC
> > > 02:00.0 [168c:0046] Atheros QCA9984 NIC
> > > 03:00.0 [168c:003c] Atheros QCA986x/988x NIC
> > >
> > > The above looks perfectly reasonable.
> > >
> > > # uboot (bad):
> > > 00.00.00 [11ab:6820] memory controller
> > > 00.01.00 [168c:002e] NIC
> > > 01.00.00 [11ab:6820] memory controller
> > > 01.01.00 [168c:0046] NIC
> > > 02.00.00 [11ab:6820] memory controller
> > > 02.01.00 [168c:003c] NIC
> > >
> > > The above looks dubious at best. Bus 00 clearly must be a root bus
> > > because bus 00 can never be a bridge's secondary bus.
> > >
> > > Either buses 01 and 02 need to also be root buses (e.g., if we had
> > > three host bridges, one leading to bus 00, another to bus 01, and
> > > another to bus 02), OR there must be Root Ports that act as bridges
> > > leading from bus 00 to bus 01 and bus 02.
> > There are 3 independent links from CPU, so 3 independent buses. Buses 01
> > and 02 are accessed directly, not via bus 00.
> That sounds like the "three host bridges leading to three root buses"
> scenario. If the NICs are ordinary endpoints (not Root Complex
> integrated endpoints), there must be a Root Port on each root bus, and
> the Root Port and the endpoint must be on different buses (just like
> any other bridge).
> For example, you could have this (which seems to be what you describe
> host bridge A to domain 0000 [bus 00-01]:
> 00:00.0 Root Port to [bus 01]
> 01:00.0 Atheros AR9287 NIC
> host bridge B to domain 0000 [bus 02-03]:
> 02:00.0 Root Port to [bus 03]
> 03:00.0 Atheros QCA9984 NIC
> host bridge C to domain 0000 [bus 04-05]:
> 04:00.0 Root Port to [bus 05]
> 05:00.0 Atheros QCA986x/988x NIC
Yes, this basically matches kernel dmesg/lspci output. These root ports
are implemented and emulated by pci-bridge-emul.c driver. Just that all
root ports are on "virtual" bus 0.
> Or, since each host bridge spawns a separate PCI hierarchy, you could
> have each one in its own domain. If the host bridges are truly
> independent, this is probably a software choice and could look like
> host bridge A to domain 0000 [bus 00-ff]:
> 0000:00:00.0 Root Port to [bus 01]
> 0000:01:00.0 Atheros AR9287 NIC
> host bridge B to domain 0001 [bus 00-ff]:
> 0001:00:00.0 Root Port to [bus 01]
> 0001:01:00.0 Atheros QCA9984 NIC
> host bridge C to domain 0002 [bus 00-ff]:
> 0002:00:00.0 Root Port to [bus 01]
> 0002:01:00.0 Atheros QCA986x/988x NIC
Yes, it is just a software choice and seems that pci-bridge-emul.c puts
all these root ports to the same linux domain. But I do not see reason
if pci-bridge-emul.c could not be programmed to put all devices into
separate segments / domains.
> > Linux devices 00:01.0, 00:02.0 and 00:03.0 are just virtual devices
> > created by kernel pci-bridge-emul.c driver. They are not real devices,
> > they are not present on PCIe bus and therefore they cannot be visible or
> > available in u-boot.
> If the NICs are ordinary PCIe endpoints there must be *something* to
> terminate the other end of the link. Maybe it has some sort of
> non-standard programming interface, but from a PCIe topology point of
> view, it's a root port.
> I don't think I can contribute anything to the stuff below. It sounds
> like there's some confusion about how to handle these root ports that
> aren't exactly root ports. That's really up to uboot and the mvebu
> driver to figure out.
Yes, I understand, it is non-standard and since beginning I'm also
confused how this stuff work at all... And this is also reason why
kernel emulates those root ports (via virtual PCIe bridge devices) to
present "standard" topology.
Remaining question is: should really kernel filter that "memory
controller" device and do not show it in linux PCIe device hierarchy?
> > Moreover kernel pci-mvebu.c controller driver filters exactly one device
> > at every bus which results that "memory controller" is not visible in
> > lspci.
> > Moreover there is mvebu specific register which seems to set device
> > number on which is present this "memory controller". U-Boot sets this
> > register to zero, so at XX:00.00 is "memory controller" and on XX:01.00
> > is wifi card. Kernel sets this register to one, so at XX:01.00 is
> > "memory controller" and on XX:00.00 is wifi card. Kernel then filter
> > config read/write access to BDF XX:01.YY address.
> > > The "memory controllers"
> > > are vendor/device ID [11ab:6820], which Linux thinks are Root Ports,
> > > so I assume they are really Root Ports (or some emulation of them).
> > This is just coincidence that memory controller visible in PCIe config
> > space has same PCI device id as virtual root bridge emulated by kernel
> > pci-bridge-emul.c driver. These are totally different devices.
> > > It's *possible* to have both a Root Port and a NIC on bus 0, as shown
> > > here. However, the NIC would have to be a Root Complex integrated
> > > Endpoint, and this NIC ([168c:002e]) is not one of those.
> > This is ordinary PCIe wifi card. It does not have integrated Root
> > Complex. Moreover that "memory controller" device is visible (in u-boot)
> > also when I disconnect wifi card.
> > > It's a
> > > garden-variety PCIe legacy endpoint connected by a link. So this NIC
> > > cannot actually be on bus 00.
> > >
> > > All these NICs are PCIe legacy endpoints with links, so they all must
> > > have a Root Port leading to them. So this topology is not really
> > > possible.
> > >
> > > # uboot (ok):
> > > 00.00.00 [168c:002e] NIC
> > > 01.00.00 [168c:0046] NIC
> > > 02.00.00 [168c:003c] NIC
> > >
> > > This topology is impossible from a PCI perspective because there's no
> > > way to get from bus 00 to bus 01 or 02.
> > This matches linux lspci output, just first bus is indexed from zero
> > instead of one. In linux it is indexed from one because at zero is that
> > fake/virtual bridge device emulated by linux kernel.
> > Does it make a little more sense now?
next prev parent reply other threads:[~2021-06-02 21:13 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210602110703.ymdt6nxsjl7e6glk@pali>
2021-06-02 19:14 ` [EXT] Re: pci mvebu issue (memory controller) Bjorn Helgaas
2021-06-02 20:39 ` Pali Rohár
2021-06-02 21:01 ` Bjorn Helgaas
2021-06-02 21:13 ` Pali Rohár [this message]
2021-06-02 21:59 ` Marek Behún
2021-02-09 13:17 Marek Behún
2021-02-10 8:54 ` Thomas Petazzoni
2021-02-10 13:59 ` [EXT] " Stefan Chulski
2021-02-19 17:44 ` Pali Rohár
2021-03-04 18:29 ` Bjorn Helgaas
2021-11-01 18:07 ` Jason Gunthorpe
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