From: kernel test robot <lkp@intel.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
lorenzo.pieralisi@arm.com, robh@kernel.org, bhelgaas@google.com
Cc: kbuild-all@lists.01.org, bjorn.andersson@linaro.org,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Siddartha Mohanadoss <smohanad@codeaurora.org>
Subject: Re: [PATCH 2/3] PCI: dwc: Add Qualcomm PCIe Endpoint controller driver
Date: Wed, 2 Jun 2021 22:05:23 +0800 [thread overview]
Message-ID: <202106022242.E6YCFfN0-lkp@intel.com> (raw)
In-Reply-To: <20210602120752.46154-3-manivannan.sadhasivam@linaro.org>
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Hi Manivannan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on robh/for-next linus/master v5.13-rc4 next-20210602]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Manivannan-Sadhasivam/Add-Qualcomm-PCIe-Endpoint-driver-support/20210602-200949
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: alpha-allyesconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/c61e07facdc420a695654c60f2f32437c93427e5
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Manivannan-Sadhasivam/Add-Qualcomm-PCIe-Endpoint-driver-support/20210602-200949
git checkout c61e07facdc420a695654c60f2f32437c93427e5
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=alpha
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-qcom-ep.c: In function 'qcom_pcie_ep_configure_tcsr':
>> drivers/pci/controller/dwc/pcie-qcom-ep.c:177:6: warning: variable 'reg' set but not used [-Wunused-but-set-variable]
177 | u32 reg;
| ^~~
drivers/pci/controller/dwc/pcie-qcom-ep.c: In function 'qcom_pcie_establish_link':
drivers/pci/controller/dwc/pcie-qcom-ep.c:357:21: warning: unused variable 'epf_bar' [-Wunused-variable]
357 | struct pci_epf_bar epf_bar;
| ^~~~~~~
drivers/pci/controller/dwc/pcie-qcom-ep.c:356:18: warning: unused variable 'epc' [-Wunused-variable]
356 | struct pci_epc *epc = pci->ep.epc;
| ^~~
vim +/reg +177 drivers/pci/controller/dwc/pcie-qcom-ep.c
169
170 /*
171 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
172 * device reset during host reboot and hibernation. The driver is
173 * expected to handle this situation.
174 */
175 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
176 {
> 177 u32 reg;
178
179 reg = readl(pcie_ep->tcsr + TCSR_PCIE_PERST_EN);
180 writel_relaxed(0x0, pcie_ep->tcsr + TCSR_PCIE_PERST_EN);
181
182 reg = readl(pcie_ep->tcsr + TCSR_PERST_SEPARATION_ENABLE);
183 writel_relaxed(0x0, pcie_ep->tcsr + TCSR_PERST_SEPARATION_ENABLE);
184 }
185
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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next prev parent reply other threads:[~2021-06-02 14:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 12:07 [PATCH 0/3] Add Qualcomm PCIe Endpoint driver support Manivannan Sadhasivam
2021-06-02 12:07 ` [PATCH 1/3] dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller Manivannan Sadhasivam
2021-06-02 14:22 ` Rob Herring
2021-06-02 14:37 ` Manivannan Sadhasivam
2021-06-02 12:07 ` [PATCH 2/3] PCI: dwc: Add Qualcomm PCIe Endpoint controller driver Manivannan Sadhasivam
2021-06-02 14:05 ` kernel test robot [this message]
2021-06-02 12:07 ` [PATCH 3/3] MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding Manivannan Sadhasivam
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