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Wed, 16 Jun 2021 17:36:48 +0000 Received: from DM6PR12MB5520.namprd12.prod.outlook.com ([fe80::18b7:5b87:86c1:afdb]) by DM6PR12MB5520.namprd12.prod.outlook.com ([fe80::18b7:5b87:86c1:afdb%8]) with mapi id 15.20.4242.019; Wed, 16 Jun 2021 17:36:48 +0000 Date: Wed, 16 Jun 2021 14:36:46 -0300 From: Jason Gunthorpe To: Lorenzo Pieralisi Cc: Will Deacon , Vikram Sethi , vidyas@nvidia.com, treding@nvidia.com, Jon Masters , Jeremy Linton , mark.rutland@arm.com, linux-pci@vger.kernel.org, sudeep.holla@arm.com, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, bhelgaas@google.com, linux-arm-kernel@lists.infradead.org, ebrower@nvidia.com, jcm@redhat.com, Grant.Likely@arm.com Subject: Re: [PATCH] arm64: PCI: Enable SMC conduit Message-ID: <20210616173646.GA1840163@nvidia.com> References: <20210105045735.1709825-1-jeremy.linton@arm.com> <20210107181416.GA3536@willie-the-truck> <56375cd8-8e11-aba6-9e11-1e0ec546e423@jonmasters.org> <20210108103216.GA17931@e121166-lin.cambridge.arm.com> <20210122194829.GE25471@willie-the-truck> <20210126225351.GA30941@willie-the-truck> <20210325131231.GA18590@e121166-lin.cambridge.arm.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?mlfCfSHnykJwo4Jt/akn/EIGF25dCCJf1DU/Yv3sYEQeWPA6nz0CxauEo7F6?= =?us-ascii?Q?c1gxti5qy1FMRVYPpw6/l9tQaqOJCzd8C2RPCRu5m4Jxnmy2HIx0tCckXey2?= =?us-ascii?Q?OkK8J4QLCulMAz0ShxlmouOkbOnEc9MuA0z0aquVvfX1LJZsrrrv/7keR/+T?= =?us-ascii?Q?AuE6mbUUbQMetf6OlIcWD0nb/VDtFlbolwBtax45zuappxXMibVJC8Vd8YxR?= =?us-ascii?Q?YnBB4TMWuircasTnkM4wlixrEDolYAWLHvdRk6fh70ZS5ERHH3ZMdpYvvfg5?= =?us-ascii?Q?1xeRfWWDxorgnX85xcImPwcfd756r8X78NdarqPKrfrhHZ6wsA3mRXlfUj8/?= =?us-ascii?Q?rPaZXTmaApy6VSs+fmrFz2MdiZidBp0iyCFmJwu0kosgpg8vKfJFVVjMSefu?= =?us-ascii?Q?jwjAxaJ77z1+56+rxo0IK8be/xnrC7Ht6NOBwyen+N2YzAtROcyx5dv6k5v6?= =?us-ascii?Q?p2P+AE/85Lvq3sL8wJ3hM2vdSoatLKyKRaDQI3XcbRHTKq7ynVz3pryJueGJ?= =?us-ascii?Q?fBy2qWb5jIB8AlhbKqMnzTh5tfwOQz9qnTHPSUpN/FKeGXNYdXrRLbD0CMrb?= =?us-ascii?Q?GrtEJ7b1cCt1B5Gfi3RqawoZTUEvftlFH80Et2nECik9TTXiyfeqUsbOGigx?= =?us-ascii?Q?4iAp2Vz9v9NglcTCBk2zW5/LmWS/2L+Fpds7RKj1IutNiitBTzD5E9JZXZnF?= =?us-ascii?Q?OIoxP+x2zMGskF/rIDb5IKYGm7B188PaCsi9TYk+vtDfb+neYGSY00U6g+vR?= =?us-ascii?Q?ZcJOzZ6xQWLc4puq49KtEI/FwEtV0KeKW8qofTT9lauPyx5SMhxoJbDMVi9I?= =?us-ascii?Q?gn0LQnWs0cGx8yUSDiGixRy8LUeokUg91dpaW6OCWJY3Aut6rmW93HNRgHMy?= =?us-ascii?Q?rX2nivtsid9WL7mTp4+/D33JKMp8/kKAEde7BTJpNpaLFlnidNz15KgHuuJO?= =?us-ascii?Q?T+9VQJrm6deUuOWXl5AC0FPr5qjb493D2Fo1wELFAG+LaU+RJFKDxul73E1n?= =?us-ascii?Q?CelHcG5j10/h7N+26Su0aVI48YAAPBCFU6COhXiiyhSjynF46ry1Q8ZY0LPW?= =?us-ascii?Q?6qXQwbyjtiBq5u/fsLD/vih5sR/d5cn2lkuVeR0GAUOUcoAIu5BKdZgbATod?= =?us-ascii?Q?qQqlhW4iGc4iyoszhpm9h3x08Qj9qLdCCYwXGNESd7SWLkZ6Ub0Jz7AFO+xK?= =?us-ascii?Q?UESoRez8S6beiQ8zwwJl+7Z+LFol500G7SEnsQM3xLpy/wtmqAUIMsk3gbR4?= =?us-ascii?Q?LSHOiVWPkCdcXliUVq5fG8zr6W/e0Fvo7asO1gumw0nlaK5m2/WM+JjOYVMQ?= =?us-ascii?Q?MZV9U8/OaU0oHIoHsTAgJvYq?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 44efcb88-9f6c-47e5-0ae5-08d930ed5135 X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB5520.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2021 17:36:47.9689 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Of1jpIenxD2LxMU4kLHARFc/XMiNmGYc4CxaPKw2OsY0NuwKG0M74jN9mi4PuqTW X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5446 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, Mar 25, 2021 at 01:12:31PM +0000, Lorenzo Pieralisi wrote: > A discussion was held between me, Will Deacon, Bjorn Helgaas and Jon > Masters to agree on a proposed solution for this matter, a summary of the > outcome below: > > - The PCI SMC conduit and related specifications are seen as firmware > kludge to a long-standing HW compliance issue. The SMC interface does > not encourage Arm partners to fix their IPs and its only purpose > consists in papering over HW issues that should have been fixed by > now; were the PCI SMC conduit introduced at arm64 ACPI inception as > part of the standardization effort the matter would have been different > but introducing it now brings about more shortcomings than benefits on > balance, especially if MCFG quirks can be controlled and monitored (and > they will). I wanted to inject a slightly different viewpoint on this (old thread, since it was revisited in some other forum) - I'm not so interested in this firmware interface to fix ECAM compliance/quirks/etc. However, in modern server type systems the PCI config space is often a software fiction being created by firmware throughout the PCI space. This has become necessary as the config space has exploded in size and complexity and PCI devices themselves have become very, very complicated. Not just the config space of single devices, but even bridges and topology are SW created in some cases. HW that is doing this is already trapping the config cycles somehow, presumably with some very ugly way like x86's SMM. Allowing a designed in way to inject software into the config space cycles does sound a lot cleaner and better to me. For instance it may solve other pain points if ARM systems had a cheap way to emulate up a "PCI device" to wrapper around some IP blob on chip. The x86 world has really driven this approach where everything on SOC is PCI discoverable, and it does seem to work well. IMHO SW emulation of config space is an important ingredient to do this. Jason