From: Artem Lapkin <email2tema@gmail.com>
To: narmstrong@baylibre.com
Cc: yue.wang@Amlogic.com, khilman@baylibre.com,
lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com,
jbrunet@baylibre.com, christianshewitt@gmail.com,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
art@khadas.com, nick@khadas.com, gouwa@khadas.com
Subject: [PATCH 4/4] PCI: loongson move mrrs quirk to core
Date: Sat, 19 Jun 2021 14:39:52 +0800 [thread overview]
Message-ID: <20210619063952.2008746-5-art@khadas.com> (raw)
In-Reply-To: <20210619063952.2008746-1-art@khadas.com>
Replace dublicated functionality loongson_mrrs_quirk to mrrs_limit_quirk
from core pci quirks
Signed-off-by: Artem Lapkin <art@khadas.com>
---
drivers/pci/controller/pci-loongson.c | 42 ++-------------------------
1 file changed, 3 insertions(+), 39 deletions(-)
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index 48169b1e3..5a54faf10 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -13,10 +13,6 @@
#include "../pci.h"
/* Device IDs */
-#define DEV_PCIE_PORT_0 0x7a09
-#define DEV_PCIE_PORT_1 0x7a19
-#define DEV_PCIE_PORT_2 0x7a29
-
#define DEV_LS2K_APB 0x7a02
#define DEV_LS7A_CONF 0x7a10
#define DEV_LS7A_LPC 0x7a0c
@@ -38,11 +34,11 @@ static void bridge_class_quirk(struct pci_dev *dev)
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
- DEV_PCIE_PORT_0, bridge_class_quirk);
+ PCI_DEVICE_ID_LOONGSON_PCIE_PORT_0, bridge_class_quirk);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
- DEV_PCIE_PORT_1, bridge_class_quirk);
+ PCI_DEVICE_ID_LOONGSON_PCIE_PORT_1, bridge_class_quirk);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
- DEV_PCIE_PORT_2, bridge_class_quirk);
+ PCI_DEVICE_ID_LOONGSON_PCIE_PORT_2, bridge_class_quirk);
static void system_bus_quirk(struct pci_dev *pdev)
{
@@ -60,38 +56,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DEV_LS7A_LPC, system_bus_quirk);
-static void loongson_mrrs_quirk(struct pci_dev *dev)
-{
- struct pci_bus *bus = dev->bus;
- struct pci_dev *bridge;
- static const struct pci_device_id bridge_devids[] = {
- { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
- { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
- { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
- { 0, },
- };
-
- /* look for the matching bridge */
- while (!pci_is_root_bus(bus)) {
- bridge = bus->self;
- bus = bus->parent;
- /*
- * Some Loongson PCIe ports have a h/w limitation of
- * 256 bytes maximum read request size. They can't handle
- * anything larger than this. So force this limit on
- * any devices attached under these ports.
- */
- if (pci_match_id(bridge_devids, bridge)) {
- if (pcie_get_readrq(dev) > 256) {
- pci_info(dev, "limiting MRRS to 256\n");
- pcie_set_readrq(dev, 256);
- }
- break;
- }
- }
-}
-DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
-
static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
unsigned int devfn, int where)
{
--
2.25.1
next prev parent reply other threads:[~2021-06-19 6:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-19 6:39 [PATCH 0/4] PCI: replace dublicated MRRS limit quirks Artem Lapkin
2021-06-19 6:39 ` [PATCH 1/4] PCI: move Keystone and Loongson device IDs to pci_ids Artem Lapkin
2021-06-19 6:39 ` [PATCH 2/4] PCI: core: quirks: add mrrs_limit_quirk Artem Lapkin
2021-07-01 17:07 ` Rob Herring
2021-06-19 6:39 ` [PATCH 3/4] PCI: keystone move mrrs quirk to core Artem Lapkin
2021-06-19 6:39 ` Artem Lapkin [this message]
2021-07-01 15:46 ` [PATCH 0/4] PCI: replace dublicated MRRS limit quirks Bjorn Helgaas
2021-07-02 1:15 ` 陈华才
2021-07-05 8:35 ` Art Nikpal
2021-07-05 22:34 ` Krzysztof Wilczynski
2021-07-06 1:36 ` Huacai Chen
2021-07-06 6:06 ` Art Nikpal
2021-07-06 9:54 ` Neil Armstrong
2021-07-07 15:54 ` Bjorn Helgaas
2021-07-07 16:43 ` Neil Armstrong
2021-07-07 16:57 ` Bjorn Helgaas
2021-07-07 17:21 ` Bjorn Helgaas
2021-07-12 9:08 ` Art Nikpal
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