From: Bjorn Helgaas <helgaas@kernel.org>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: "Art Nikpal" <email2tema@gmail.com>,
"Huacai Chen" <chenhuacai@gmail.com>,
陈华才 <chenhuacai@loongson.cn>, "Yue Wang" <yue.wang@amlogic.com>,
"Kevin Hilman" <khilman@baylibre.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczynski" <kw@linux.com>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Christian Hewitt" <christianshewitt@gmail.com>,
"Martin Blumenstingl" <martin.blumenstingl@googlemail.com>,
PCI <linux-pci@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
"open list:ARM/Amlogic Meson..."
<linux-amlogic@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
"Artem Lapkin" <art@khadas.com>, "Nick Xie" <nick@khadas.com>,
"Gouwa Wang" <gouwa@khadas.com>
Subject: Re: [PATCH 0/4] PCI: replace dublicated MRRS limit quirks
Date: Wed, 7 Jul 2021 10:54:18 -0500 [thread overview]
Message-ID: <20210707155418.GA897940@bjorn-Precision-5520> (raw)
In-Reply-To: <1271fa28-dddd-01a3-5ad5-e3b4898f5482@baylibre.com>
On Tue, Jul 06, 2021 at 11:54:05AM +0200, Neil Armstrong wrote:
> In their Designware PCIe controller driver, amlogic sets the
> Max_Payload_Size & Max_Read_Request_Size to 256:
> https://elixir.bootlin.com/linux/latest/source/drivers/pci/controller/dwc/pci-meson.c#L260
> https://elixir.bootlin.com/linux/latest/source/drivers/pci/controller/dwc/pci-meson.c#L276
> in their root port PCIe Express Device Control Register.
>
> Looking at the Synopsys DW-PCIe Databook, Max_Payload_Size &
> Max_Read_Request_Size are used to decompose into AXI burst, but it
> seems the Max_Payload_Size & Max_Read_Request_Size are set by
> default to 512 but the internal Max_Payload_Size_Supported is set to
> 256, thus changing these values to 256 at runtime to match and
> optimize bandwidth.
>
> It's said, "Reducing Outbound Decomposition" :
> - "Ensure that your application master does not generate bursts of
> size greater than or equal to Max_Payload_Size"
>
> - "Program your PCIe system with a larger value of Max_Payload_Size
> without exceeding Max_Payload_Size_Supported"
>
> - "Program your PCIe system with a larger value of Max_Read_Request
> without exceeding Max_Payload_Size_Supported:
>
> So leaving 512 in Max_Payload_Size & Max_Read_Request leads to
> Outbound Decomposition which decreases PCIe link and degrades the
> AXI bus by doubling the bursts, leading to this fix to avoid
> overflowing the AXI bus.
>
> So it seems to be still needed, I assume this *should* be handled in
> the core somehow to propagate these settings to child endpoints to
> match the root port Max_Payload_Size & Max_Read_Request sizes.
>
> Maybe by adding a core function to set these values instead of using
> the dw_pcie_find_capability() & dw_pcie_write/readl_dbi() helpers
> and set a state on the root port to propagate the value ?
I don't have the Synopsys DW-PCIe Databook, so I'm lacking any
context. The above *seems* to say that MPS/MRRS settings affect AXI
bus usage.
The MPS and MRRS registers are defined to affect traffic on *PCIe*. If
a platform uses MPS and MRRS values to optimize transfers on non-PCIe
links, that's a problem because the PCI core code that manages MPS and
MRRS has no knowledge of those non-PCIe parts of the system.
You might be able to deal with this in Synopsys-specific code somehow,
but it's going to be a bit of a hassle because I don't want it to make
maintenance of the generic MPS/MRRS code harder.
Bjorn
next prev parent reply other threads:[~2021-07-07 15:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-19 6:39 [PATCH 0/4] PCI: replace dublicated MRRS limit quirks Artem Lapkin
2021-06-19 6:39 ` [PATCH 1/4] PCI: move Keystone and Loongson device IDs to pci_ids Artem Lapkin
2021-06-19 6:39 ` [PATCH 2/4] PCI: core: quirks: add mrrs_limit_quirk Artem Lapkin
2021-07-01 17:07 ` Rob Herring
2021-06-19 6:39 ` [PATCH 3/4] PCI: keystone move mrrs quirk to core Artem Lapkin
2021-06-19 6:39 ` [PATCH 4/4] PCI: loongson " Artem Lapkin
2021-07-01 15:46 ` [PATCH 0/4] PCI: replace dublicated MRRS limit quirks Bjorn Helgaas
2021-07-02 1:15 ` 陈华才
2021-07-05 8:35 ` Art Nikpal
2021-07-05 22:34 ` Krzysztof Wilczynski
2021-07-06 1:36 ` Huacai Chen
2021-07-06 6:06 ` Art Nikpal
2021-07-06 9:54 ` Neil Armstrong
2021-07-07 15:54 ` Bjorn Helgaas [this message]
2021-07-07 16:43 ` Neil Armstrong
2021-07-07 16:57 ` Bjorn Helgaas
2021-07-07 17:21 ` Bjorn Helgaas
2021-07-12 9:08 ` Art Nikpal
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