From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F338C4320A for ; Tue, 3 Aug 2021 04:26:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 117FC60EFD for ; Tue, 3 Aug 2021 04:26:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233719AbhHCE0G (ORCPT ); Tue, 3 Aug 2021 00:26:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:35104 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234056AbhHCEZr (ORCPT ); Tue, 3 Aug 2021 00:25:47 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E149561158; Tue, 3 Aug 2021 04:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627964736; bh=SkJpApRxFG/jXxtvFIyQH90yLQk7myOrmz5Wih/Vuyw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=awMZtxBCR6GUxLWOagGdN/FDay6Jkz15CQMKxFG2yTgIVUsUx6vsnK4JcbxpWjx+1 kQlCkP6FyuwBM9ub3ON2S7ZlW9f6TjNRAwq+9Q0EaM6rh4Iu38cnCwt5hUjIPJPc0k Ci84LWZzZ8CPkAXX0/HqHVO0n6U8fiiksBaVVgjBF1ZiMPygfuk7eOwfZNz5vmCpGx 7MgVnlsV0tv6tKMWYwZtuCn60lFP+MPUOPsqjlelHwIjM2MtAGF/fgHqBuKmc0sDVK X1c69ifh+ndYVuRVbQ2B0qXpp745y3R1qrUx+UZnOEIN4HzEbUgKnfcx+K3Lwlt/aK IsMAS/UCBLbpA== Date: Tue, 3 Aug 2021 06:25:28 +0200 From: Mauro Carvalho Chehab To: Manivannan Sadhasivam Cc: Vinod Koul , Bjorn Helgaas , Rob Herring , linuxarm@huawei.com, mauro.chehab@huawei.com, Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Binghui Wang , Lorenzo Pieralisi , Rob Herring , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v7 08/10] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Message-ID: <20210803062528.0a264682@coco.lan> In-Reply-To: <20210724041150.GA4053@thinkpad> References: <20210722133628.GC4446@workstation> <20210723085318.243f155f@coco.lan> <20210724041150.GA4053@thinkpad> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Em Sat, 24 Jul 2021 09:41:50 +0530 Manivannan Sadhasivam escreveu: > On Fri, Jul 23, 2021 at 08:53:18AM +0200, Mauro Carvalho Chehab wrote: > > Em Thu, 22 Jul 2021 19:06:28 +0530 > > Manivannan Sadhasivam escreveu: > > > > > On Wed, Jul 21, 2021 at 10:39:10AM +0200, Mauro Carvalho Chehab wrote: > > > > From: Manivannan Sadhasivam > > > > > > > > Add DTS bindings for the HiKey 970 board's PCIe hardware. > > > > > > > > Co-developed-by: Mauro Carvalho Chehab > > > > Signed-off-by: Manivannan Sadhasivam > > > > Signed-off-by: Mauro Carvalho Chehab > > > > --- > > > > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++ > > > > .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - > > > > drivers/pci/controller/dwc/pcie-kirin.c | 12 ---- > > > > 3 files changed, 71 insertions(+), 13 deletions(-) > > > > > > > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > > > > index 1f228612192c..6dfcfcfeedae 100644 > > > > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > > > > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > > > > @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { > > > > #clock-cells = <1>; > > > > }; > > > > > > > > + pmctrl: pmctrl@fff31000 { > > > > + compatible = "hisilicon,hi3670-pmctrl", "syscon"; > > > > + reg = <0x0 0xfff31000 0x0 0x1000>; > > > > + #clock-cells = <1>; > > > > + }; > > > > + > > > > > > Irrelevant change to this patch. > > > > Huh? > > > > This is used by PCIe PHY, as part of the power on procedures: > > > > +static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) > > +{ > > + struct device *dev = phy->dev; > > + u32 time = 100; > > + unsigned int val = NOC_PW_MASK; > > + int rst; > > + > > + if (enable) > > + val = NOC_PW_MASK | NOC_PW_SET_BIT; > > + else > > + val = NOC_PW_MASK; > > + rst = enable ? 1 : 0; > > + > > + regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val); > > > > > > Ah... you're hardcoding the syscon compatible in driver. Sorry missed that. > > But if these syscon nodes are independent memory regions or belong to non > PCI/PHY memory map, you could've fetched the reference through a DT property > along with the offset then used it in driver. > > Like, > > pcie_phy: pcie-phy@fc000000 { > ... > hisilicon,noc-power-regs = <&pmctrl 0x38c>; > hisilicon,sctrl-cmos-regs = <&sctrl 0x60>; > ... > }; > > The benefit of doing this way is, if the pmctrl, sctrl register layout changes > in future, you can handle it without any issues. Interesting approach, but probably overkill. I mean, the register mapping here should be the same for all Kirin 970 PHY based devices. A PHY for a different SoC will likely have other differences than just those two regs. Regards, Mauro