* [PATCH V7 0/5] PCI: Loongson pci improvements and quirks
@ 2021-08-20 9:52 Huacai Chen
2021-08-20 9:52 ` [PATCH V7 1/5] PCI: loongson: Use correct pci config access operations Huacai Chen
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Huacai Chen @ 2021-08-20 9:52 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, Xuefeng Li, Huacai Chen, Jiaxun Yang, Huacai Chen,
Jianmin Lv, Tiezhu Yang
This patchset improves Loongson PCI controller driver and resolves some
problems: LS2K/LS7A's PCI config space supports 1/2/4-bytes access, so
the first patch use pci_generic_config_read()/pci_generic_config_write()
for them; the second patch add ACPI init support which will be used by
LoongArch; the third patch improves the mrrs quirk for LS7A chipset; The
fourth patch add a new quirk for LS7A chipset to avoid poweroff/reboot
failure, and the fifth patch add a new quirk for LS7A chipset to fix the
multifunction devices' irq pin mappings.
V1 -> V2:
1, Rework the 4th patch;
2, Improve commit messages;
3, Remove the last patch since there is better solutions.
V2 -> V3:
1, Add more affected device ids for the 4th patch;
2, Improve commit messages to describe root causes.
V3 -> V4:
1, Rework the MRRS quirk patch;
2, Improve commit messages to describe root causes, again.
V4 -> V5:
1, Improve the MRRS quirk patch;
2, Change the order of 2nd and 3rd patch;
3, Improve commit messages to describe root causes, again.
V5 -> V6:
1, Rework the 1st patch;
2, Adjust the order of the series.
V6 -> V7:
1, Use correct pci config access operations;
2, Add ACPI init support for LoongArch;
3, Don't move to quirks.c since the driver has ACPI support;
4, Some other minor improvements.
Huacai Chen, Tiezhu Yang and Jianmin Lv(5):
PCI: loongson: Use correct pci config access operations.
PCI: loongson: Add ACPI init support.
PCI: Improve the MRRS quirk for LS7A.
PCI: Add quirk for LS7A to avoid reboot failure.
PCI: Add quirk for multifunction devices of LS7A.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
drivers/acpi/pci_mcfg.c | 13 +++
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pci-loongson.c | 162 +++++++++++++++++++++++++++-------
drivers/pci/pci.c | 6 ++
drivers/pci/pcie/portdrv_core.c | 6 +-
include/linux/pci-ecam.h | 1 +
include/linux/pci.h | 2 +
7 files changed, 158 insertions(+), 34 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V7 1/5] PCI: loongson: Use correct pci config access operations
2021-08-20 9:52 [PATCH V7 0/5] PCI: Loongson pci improvements and quirks Huacai Chen
@ 2021-08-20 9:52 ` Huacai Chen
2021-08-20 9:52 ` [PATCH V7 2/5] PCI: loongson: Add ACPI init support Huacai Chen
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2021-08-20 9:52 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, Xuefeng Li, Huacai Chen, Jiaxun Yang, Huacai Chen
LS2K/LS7A support 8/16/32-bits pci config access operations, so we can
safely use pci_generic_config_read()/pci_generic_config_write() instead
of pci_generic_config_read32()/pci_generic_config_write32().
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
drivers/pci/controller/pci-loongson.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index 48169b1e3817..7140bdd04d35 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -159,8 +159,15 @@ static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
return val;
}
-/* H/w only accept 32-bit PCI operations */
+/* LS2K/LS7A accept 8/16/32-bit PCI operations */
static struct pci_ops loongson_pci_ops = {
+ .map_bus = pci_loongson_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+};
+
+/* RS780/SR5690 only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops32 = {
.map_bus = pci_loongson_map_bus,
.read = pci_generic_config_read32,
.write = pci_generic_config_write32,
@@ -218,8 +225,11 @@ static int loongson_pci_probe(struct platform_device *pdev)
}
bridge->sysdata = priv;
- bridge->ops = &loongson_pci_ops;
bridge->map_irq = loongson_map_irq;
+ if (!of_device_is_compatible(node, "loongson,rs780e-pci"))
+ bridge->ops = &loongson_pci_ops;
+ else
+ bridge->ops = &loongson_pci_ops32;
return pci_host_probe(bridge);
}
--
2.27.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 2/5] PCI: loongson: Add ACPI init support
2021-08-20 9:52 [PATCH V7 0/5] PCI: Loongson pci improvements and quirks Huacai Chen
2021-08-20 9:52 ` [PATCH V7 1/5] PCI: loongson: Use correct pci config access operations Huacai Chen
@ 2021-08-20 9:52 ` Huacai Chen
2021-08-20 9:52 ` [PATCH V7 3/5] PCI: Improve the MRRS quirk for LS7A Huacai Chen
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2021-08-20 9:52 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, Xuefeng Li, Huacai Chen, Jiaxun Yang, Huacai Chen
Loongson PCH (LS7A chipset) will be used by both MIPS-based and
LoongArch-based Loongson processors. MIPS-based Loongson uses FDT
while LoongArch-base Loongson uses ACPI, this patch add ACPI init
support for the driver in drivers/pci/controller/pci-loongson.c
because it is currently FDT-only.
LoongArch is a new RISC ISA, mainline support will come soon, and
documentations are here (in translation):
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
drivers/acpi/pci_mcfg.c | 13 +++++++
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pci-loongson.c | 54 ++++++++++++++++++++++++++-
include/linux/pci-ecam.h | 1 +
4 files changed, 67 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 53cab975f612..860014b89b8e 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -41,6 +41,8 @@ struct mcfg_fixup {
static struct mcfg_fixup mcfg_quirks[] = {
/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
+#ifdef CONFIG_ARM64
+
#define AL_ECAM(table_id, rev, seg, ops) \
{ "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
@@ -169,6 +171,17 @@ static struct mcfg_fixup mcfg_quirks[] = {
ALTRA_ECAM_QUIRK(1, 13),
ALTRA_ECAM_QUIRK(1, 14),
ALTRA_ECAM_QUIRK(1, 15),
+#endif /* ARM64 */
+
+#ifdef CONFIG_LOONGARCH
+#define LOONGSON_ECAM_MCFG(table_id, seg) \
+ { "LOONGS", table_id, 1, seg, MCFG_BUS_ANY, &loongson_pci_ecam_ops }
+
+ LOONGSON_ECAM_MCFG("\0", 0),
+ LOONGSON_ECAM_MCFG("LOONGSON", 0),
+ LOONGSON_ECAM_MCFG("\0", 1),
+ LOONGSON_ECAM_MCFG("LOONGSON", 1),
+#endif /* LOONGARCH */
};
static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 5e1e3796efa4..77aa7272425c 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -287,7 +287,7 @@ config PCI_HYPERV_INTERFACE
config PCI_LOONGSON
bool "LOONGSON PCI Controller"
depends on MACH_LOONGSON64 || COMPILE_TEST
- depends on OF
+ depends on OF || ACPI
depends on PCI_QUIRKS
default MACH_LOONGSON64
help
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index 7140bdd04d35..db5b51ebff3c 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -9,6 +9,8 @@
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
+#include <linux/pci-acpi.h>
+#include <linux/pci-ecam.h>
#include "../pci.h"
@@ -92,6 +94,18 @@ static void loongson_mrrs_quirk(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
+{
+ struct pci_config_window *cfg;
+
+ if (acpi_disabled)
+ return (struct loongson_pci *)(bus->sysdata);
+ else {
+ cfg = bus->sysdata;
+ return (struct loongson_pci *)(cfg->priv);
+ }
+}
+
static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
unsigned int devfn, int where)
{
@@ -119,8 +133,10 @@ static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devf
int where)
{
unsigned char busnum = bus->number;
- struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
- struct loongson_pci *priv = pci_host_bridge_priv(bridge);
+ struct loongson_pci *priv = pci_bus_to_loongson_pci(bus);
+
+ if (pci_is_root_bus(bus))
+ busnum = 0;
/*
* Do not read more than one device on the bus other than
@@ -141,6 +157,8 @@ static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devf
return NULL;
}
+#ifdef CONFIG_OF
+
static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
@@ -242,3 +260,35 @@ static struct platform_driver loongson_pci_driver = {
.probe = loongson_pci_probe,
};
builtin_platform_driver(loongson_pci_driver);
+
+#endif
+
+#ifdef CONFIG_ACPI
+
+static int loongson_pci_ecam_init(struct pci_config_window *cfg)
+{
+ struct device *dev = cfg->parent;
+ struct loongson_pci *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ cfg->priv = priv;
+ priv->flags = FLAG_CFG1 | FLAG_DEV_FIX,
+ priv->cfg1_base = cfg->win - (cfg->busr.start << 16);
+
+ return 0;
+}
+
+const struct pci_ecam_ops loongson_pci_ecam_ops = {
+ .bus_shift = 16,
+ .init = loongson_pci_ecam_init,
+ .pci_ops = {
+ .map_bus = pci_loongson_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+ }
+};
+
+#endif
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index adea5a4771cf..6b1301e2498e 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
+extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
#endif
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
--
2.27.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 3/5] PCI: Improve the MRRS quirk for LS7A
2021-08-20 9:52 [PATCH V7 0/5] PCI: Loongson pci improvements and quirks Huacai Chen
2021-08-20 9:52 ` [PATCH V7 1/5] PCI: loongson: Use correct pci config access operations Huacai Chen
2021-08-20 9:52 ` [PATCH V7 2/5] PCI: loongson: Add ACPI init support Huacai Chen
@ 2021-08-20 9:52 ` Huacai Chen
2021-08-20 9:52 ` [PATCH V7 4/5] PCI: Add quirk for LS7A to avoid reboot failure Huacai Chen
2021-08-20 9:52 ` [PATCH V7 5/5] PCI: Add quirk for multifunction devices of LS7A Huacai Chen
4 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2021-08-20 9:52 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, Xuefeng Li, Huacai Chen, Jiaxun Yang, Huacai Chen
In new revision of LS7A, some PCIe ports support larger value than 256,
but their maximum supported MRRS values are not detectable. Moreover,
the current loongson_mrrs_quirk() cannot avoid devices increasing its
MRRS after pci_enable_device(), and some devices (e.g. Realtek 8169)
will actually set a big value in its driver. So the only possible way
is configure MRRS of all devices in BIOS, and add a pci host bridge bit
flag (i.e., no_inc_mrrs) to stop the increasing MRRS operations.
However, according to PCIe Spec, it is legal for an OS to program any
value for MRRS, and it is also legal for an endpoint to generate a Read
Request with any size up to its MRRS. As the hardware engineers say, the
root cause here is LS7A doesn't break up large read requests. In detail,
LS7A PCIe port reports CA (Completer Abort) if it receives a Memory Read
request with a size that's "too big" ("too big" means larger than the
PCIe ports can handle, which means 256 for some ports and 4096 for the
others, and of course this is a problem in the LS7A's hardware design).
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
drivers/pci/controller/pci-loongson.c | 47 ++++++++++-----------------
drivers/pci/pci.c | 6 ++++
include/linux/pci.h | 1 +
3 files changed, 25 insertions(+), 29 deletions(-)
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index db5b51ebff3c..c4b322cae97e 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -62,37 +62,26 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DEV_LS7A_LPC, system_bus_quirk);
-static void loongson_mrrs_quirk(struct pci_dev *dev)
+static void loongson_mrrs_quirk(struct pci_dev *pdev)
{
- struct pci_bus *bus = dev->bus;
- struct pci_dev *bridge;
- static const struct pci_device_id bridge_devids[] = {
- { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
- { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
- { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
- { 0, },
- };
-
- /* look for the matching bridge */
- while (!pci_is_root_bus(bus)) {
- bridge = bus->self;
- bus = bus->parent;
- /*
- * Some Loongson PCIe ports have a h/w limitation of
- * 256 bytes maximum read request size. They can't handle
- * anything larger than this. So force this limit on
- * any devices attached under these ports.
- */
- if (pci_match_id(bridge_devids, bridge)) {
- if (pcie_get_readrq(dev) > 256) {
- pci_info(dev, "limiting MRRS to 256\n");
- pcie_set_readrq(dev, 256);
- }
- break;
- }
- }
+ /*
+ * Some Loongson PCIe ports have h/w limitations of maximum read
+ * request size. They can't handle anything larger than this. So
+ * force this limit on any devices attached under these ports.
+ */
+ struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
+
+ if (!bridge)
+ return;
+
+ bridge->no_inc_mrrs = 1;
}
-DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_0, loongson_mrrs_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_1, loongson_mrrs_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_2, loongson_mrrs_quirk);
static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
{
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index aacf575c15cf..3279da8ce2dd 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5800,6 +5800,7 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
{
u16 v;
int ret;
+ struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
return -EINVAL;
@@ -5818,6 +5819,11 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
v = (ffs(rq) - 8) << 12;
+ if (bridge->no_inc_mrrs) {
+ if (rq > pcie_get_readrq(dev))
+ return -EINVAL;
+ }
+
ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_READRQ, v);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 540b377ca8f6..e2583c2785e2 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -541,6 +541,7 @@ struct pci_host_bridge {
void *release_data;
unsigned int ignore_reset_delay:1; /* For entire hierarchy */
unsigned int no_ext_tags:1; /* No Extended Tags */
+ unsigned int no_inc_mrrs:1; /* No Increase MRRS */
unsigned int native_aer:1; /* OS may use PCIe AER */
unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
--
2.27.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 4/5] PCI: Add quirk for LS7A to avoid reboot failure
2021-08-20 9:52 [PATCH V7 0/5] PCI: Loongson pci improvements and quirks Huacai Chen
` (2 preceding siblings ...)
2021-08-20 9:52 ` [PATCH V7 3/5] PCI: Improve the MRRS quirk for LS7A Huacai Chen
@ 2021-08-20 9:52 ` Huacai Chen
2021-08-20 9:52 ` [PATCH V7 5/5] PCI: Add quirk for multifunction devices of LS7A Huacai Chen
4 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2021-08-20 9:52 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, Xuefeng Li, Huacai Chen, Jiaxun Yang, Huacai Chen
Commit cc27b735ad3a75574a ("PCI/portdrv: Turn off PCIe services during
shutdown") causes poweroff/reboot failure on systems with LS7A chipset.
We found that if we remove "pci_command &= ~PCI_COMMAND_MASTER;" in
do_pci_disable_device(), it can work well. The hardware engineer says
that the root cause is that CPU is still accessing PCIe devices while
poweroff/reboot, and if we disable the Bus Master Bit at this time, the
PCIe controller doesn't forward requests to downstream devices, and also
doesn't send TIMEOUT to CPU, which causes CPU wait forever (hardware
deadlock). This behavior is a PCIe protocol violation (Bus Master should
not be involved in CPU MMIO transactions), and it will be fixed in new
revisions of hardware (add timeout mechanism for CPU read request,
whether or not Bus Master bit is cleared).
On some x86 platforms, radeon/amdgpu devices can cause similar problems
[1][2]. Once before I wanted to make a single patch to solve "all of
these problems" together, but it seems unreasonable because maybe they
are not exactly the same problem. So, this patch just add a quirk for
LS7A to avoid clearing Bus Master bit in pcie_port_device_remove(), and
leave other platforms as is.
[1] https://bugs.freedesktop.org/show_bug.cgi?id=97980
[2] https://bugs.freedesktop.org/show_bug.cgi?id=98638
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
drivers/pci/controller/pci-loongson.c | 20 ++++++++++++++++++++
drivers/pci/pcie/portdrv_core.c | 6 +++++-
include/linux/pci.h | 1 +
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index c4b322cae97e..aaeeb14ef78a 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -83,6 +83,26 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DEV_PCIE_PORT_2, loongson_mrrs_quirk);
+static void loongson_bmaster_quirk(struct pci_dev *pdev)
+{
+ /*
+ * Some Loongson PCIe ports will cause CPU deadlock if disable
+ * the Bus Master bit during poweroff/reboot.
+ */
+ struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
+
+ if (!bridge)
+ return;
+
+ bridge->no_dis_bmaster = 1;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_0, loongson_bmaster_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_1, loongson_bmaster_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_2, loongson_bmaster_quirk);
+
static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
{
struct pci_config_window *cfg;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e1fed6649c41..7f9549a1f48b 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -486,9 +486,13 @@ EXPORT_SYMBOL_GPL(pcie_port_find_device);
*/
void pcie_port_device_remove(struct pci_dev *dev)
{
+ struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
+
device_for_each_child(&dev->dev, NULL, remove_iter);
pci_free_irq_vectors(dev);
- pci_disable_device(dev);
+
+ if (!bridge->no_dis_bmaster)
+ pci_disable_device(dev);
}
/**
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e2583c2785e2..46dfbb61f2f0 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -542,6 +542,7 @@ struct pci_host_bridge {
unsigned int ignore_reset_delay:1; /* For entire hierarchy */
unsigned int no_ext_tags:1; /* No Extended Tags */
unsigned int no_inc_mrrs:1; /* No Increase MRRS */
+ unsigned int no_dis_bmaster:1; /* No Disable Bus Master */
unsigned int native_aer:1; /* OS may use PCIe AER */
unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
--
2.27.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 5/5] PCI: Add quirk for multifunction devices of LS7A
2021-08-20 9:52 [PATCH V7 0/5] PCI: Loongson pci improvements and quirks Huacai Chen
` (3 preceding siblings ...)
2021-08-20 9:52 ` [PATCH V7 4/5] PCI: Add quirk for LS7A to avoid reboot failure Huacai Chen
@ 2021-08-20 9:52 ` Huacai Chen
4 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2021-08-20 9:52 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, Xuefeng Li, Huacai Chen, Jiaxun Yang, Jianmin Lv, Huacai Chen
From: Jianmin Lv <lvjianmin@loongson.cn>
In LS7A, multifunction device use same PCI PIN (because the PIN register
report the same INTx value to each function) but we need different IRQ
for different functions, so add a quirk to fix it for standard PCI PIN
usage.
This patch only affect ACPI based systems (and only needed by ACPI based
systems, too). For DT based systems, the irq mappings is defined in .dts
files and be handled by of_irq_parse_pci().
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
drivers/pci/controller/pci-loongson.c | 29 +++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index aaeeb14ef78a..545982ea6530 100644
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -22,6 +22,12 @@
#define DEV_LS2K_APB 0x7a02
#define DEV_LS7A_CONF 0x7a10
#define DEV_LS7A_LPC 0x7a0c
+#define DEV_LS7A_GMAC 0x7a03
+#define DEV_LS7A_DC 0x7a06
+#define DEV_LS7A_GPU 0x7a15
+#define DEV_LS7A_AHCI 0x7a08
+#define DEV_LS7A_EHCI 0x7a14
+#define DEV_LS7A_OHCI 0x7a24
#define FLAG_CFG0 BIT(0)
#define FLAG_CFG1 BIT(1)
@@ -103,6 +109,29 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
DEV_PCIE_PORT_2, loongson_bmaster_quirk);
+static void loongson_pci_pin_quirk(struct pci_dev *pdev)
+{
+ pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_DC, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_GPU, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_GMAC, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_AHCI, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_EHCI, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_OHCI, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_0, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_1, loongson_pci_pin_quirk);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_2, loongson_pci_pin_quirk);
+
static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
{
struct pci_config_window *cfg;
--
2.27.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-08-20 9:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-20 9:52 [PATCH V7 0/5] PCI: Loongson pci improvements and quirks Huacai Chen
2021-08-20 9:52 ` [PATCH V7 1/5] PCI: loongson: Use correct pci config access operations Huacai Chen
2021-08-20 9:52 ` [PATCH V7 2/5] PCI: loongson: Add ACPI init support Huacai Chen
2021-08-20 9:52 ` [PATCH V7 3/5] PCI: Improve the MRRS quirk for LS7A Huacai Chen
2021-08-20 9:52 ` [PATCH V7 4/5] PCI: Add quirk for LS7A to avoid reboot failure Huacai Chen
2021-08-20 9:52 ` [PATCH V7 5/5] PCI: Add quirk for multifunction devices of LS7A Huacai Chen
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