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Wed, 27 Oct 2021 09:57:51 +0000 From: Yishai Hadas To: , , , CC: , , , , , , , , Subject: [PATCH V5 mlx5-next 01/13] PCI/IOV: Add pci_iov_vf_id() to get VF index Date: Wed, 27 Oct 2021 12:56:46 +0300 Message-ID: <20211027095658.144468-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211027095658.144468-1-yishaih@nvidia.com> References: <20211027095658.144468-1-yishaih@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 16d097c2-279e-42d5-30eb-08d999303f51 X-MS-TrafficTypeDiagnostic: BL0PR12MB4993: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q9yfiEuse/Xqn7sWZziWJ4Ib6IxJJtVgC9XHRU53VndeOj8aGzmkNtZX+jSxL2VTyFX7gzrlEpW9HMQC+2QNTRbiGLhNhxBVJFyG4kZo6gyCsk5Cy/WZbesA97ZY2AGYk3IGvDpEV91bR5lq5QgX7PCrBz1u5eWt9rgtVFsC6hD25HaPGnPf2gYx6CJDVP4oxRwh6cK3rqWpf3Maz8cZEF0R8hps3cB6ZI4jRwv+lSCLoL57T17gzNJoO5vmzFXUdoE5+/8HogzCLYRQPyDcHcuhcGL1h0cnmrlk1QT86mxLmdz2UjfiA8a+MfxlgPAKGOeLFYCk0BGFfou3gx5Sz9iL4UduyX0VjmwEJXjmygHx4WJTtsIkGIELGlBVcBKcCIPdnlxnAIYF4c6vZLIbPjmfvf9HE7sA5/SgBiuzUamzx/OVbiV4NdnF0XKIeQVRyRWE7BzjMRXu73HPXhJdJ/Yu83xkUDOu9w/doi6nL5OKOdEgcjvgBcGxtgC+jcpyXSIV18cXGocjPH0GVdxP/DtG3WTYGI+404WF1uZoUX8JL7W7v2UtoJpGqC+vg9+gc4th09MMDLtjvE4y28z/9X9S6esNg/ta+H6fwMymnHaMxo2BTyrfNleceuZwTodCUhqK2c+Zt7faSc+sjc9iUiOjGQPkB2qNfV95uCA1NVgYzPl1oBlGHlMValblnz6Ik28ocbi+QWIBIELY6BStvA== X-Forefront-Antispam-Report: CIP:216.228.112.32;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2906002)(7696005)(82310400003)(83380400001)(7636003)(1076003)(110136005)(186003)(2616005)(8676002)(4326008)(36860700001)(5660300002)(356005)(6636002)(426003)(26005)(336012)(47076005)(70586007)(86362001)(107886003)(316002)(6666004)(508600001)(36756003)(70206006)(8936002)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 09:57:54.8172 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16d097c2-279e-42d5-30eb-08d999303f51 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4993 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jason Gunthorpe The PCI core uses the VF index internally, often called the vf_id, during the setup of the VF, eg pci_iov_add_virtfn(). This index is needed for device drivers that implement live migration for their internal operations that configure/control their VFs. Specifically, mlx5_vfio_pci driver that is introduced in coming patches from this series needs it and not the bus/device/function which is exposed today. Add pci_iov_vf_id() which computes the vf_id by reversing the math that was used to create the bus/device/function. Signed-off-by: Yishai Hadas Signed-off-by: Jason Gunthorpe Acked-by: Bjorn Helgaas Signed-off-by: Leon Romanovsky --- drivers/pci/iov.c | 14 ++++++++++++++ include/linux/pci.h | 8 +++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index dafdc652fcd0..e7751fa3fe0b 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -33,6 +33,20 @@ int pci_iov_virtfn_devfn(struct pci_dev *dev, int vf_id) } EXPORT_SYMBOL_GPL(pci_iov_virtfn_devfn); +int pci_iov_vf_id(struct pci_dev *dev) +{ + struct pci_dev *pf; + + if (!dev->is_virtfn) + return -EINVAL; + + pf = pci_physfn(dev); + return (((dev->bus->number << 8) + dev->devfn) - + ((pf->bus->number << 8) + pf->devfn + pf->sriov->offset)) / + pf->sriov->stride; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_id); + /* * Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may * change when NumVFs changes. diff --git a/include/linux/pci.h b/include/linux/pci.h index cd8aa6fce204..2337512e67f0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2153,7 +2153,7 @@ void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); #ifdef CONFIG_PCI_IOV int pci_iov_virtfn_bus(struct pci_dev *dev, int id); int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); - +int pci_iov_vf_id(struct pci_dev *dev); int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); void pci_disable_sriov(struct pci_dev *dev); @@ -2181,6 +2181,12 @@ static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) { return -ENOSYS; } + +static inline int pci_iov_vf_id(struct pci_dev *dev) +{ + return -ENOSYS; +} + static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) { return -ENODEV; } -- 2.18.1