[PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable

From: qizhong cheng <qizhong.cheng@mediatek.com>
To: "Ryder Lee" <ryder.lee@mediatek.com>,
	"Jianjun Wang" <jianjun.wang@mediatek.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyiński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Chuanjia Liu <chuanjia.liu@mediatek.com>,
	Jiey Yang <ot_jiey.yang@mediatek.com>,
	qizhong cheng <qizhong.cheng@mediatek.com>
Subject: [PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable
Date: Thu, 4 Nov 2021 14:21:44 +0800	[thread overview]
Message-ID: <20211104062144.31453-1-qizhong.cheng@mediatek.com> (raw)

Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
---
 drivers/pci/controller/pcie-mediatek.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 2f3f974977a3..b32acbac8084 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
 	 */
 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
 
+	/*
+	 * Described in PCIe CEM specification setctions 2.2 (PERST# Signal)
+	 * and 2.2.1 (Initial Power-Up (G3 to S0)).
+	 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+	 * for the power and clock to become stable.
+	 */
+	msleep(100);
+
 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
 	val = readl(port->base + PCIE_RST_CTRL);
 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
-- 
2.25.1

