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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: "Marek Behún" <kabel@kernel.org>
Cc: linux-pci@vger.kernel.org, pali@kernel.org
Subject: Re: [PATCH 2/7] PCI: pci-bridge-emul: Add definitions for missing capabilities registers
Date: Mon, 29 Nov 2021 16:44:44 +0000	[thread overview]
Message-ID: <20211129164444.GC26244@lpieralisi> (raw)
In-Reply-To: <20211031181233.9976-3-kabel@kernel.org>

On Sun, Oct 31, 2021 at 07:12:28PM +0100, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> pci-bridge-emul driver already allocates buffer for capabilities up to the
> PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
> registers. Add these missing definitions.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>
> Cc: stable@vger.kernel.org

Is this tag in preparation for something else ? I don't even think this
is a fix per-se.

Lorenzo

> ---
>  drivers/pci/pci-bridge-emul.c | 39 +++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
> index a4af1a533d71..aa3320e3c469 100644
> --- a/drivers/pci/pci-bridge-emul.c
> +++ b/drivers/pci/pci-bridge-emul.c
> @@ -251,6 +251,45 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
>  		.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
>  		.w1c = PCI_EXP_RTSTA_PME,
>  	},
> +
> +	[PCI_EXP_DEVCAP2 / 4] = {
> +		/* Device capabilities 2 register has reserved bits [30:27]. */
> +		.ro = BIT(31) | GENMASK(26, 0),
> +	},
> +
> +	[PCI_EXP_DEVCTL2 / 4] = {
> +		/*
> +		 * Device control 2 register is RW.
> +		 *
> +		 * Device status 2 register is reserved.
> +		 */
> +		.rw = GENMASK(15, 0),
> +	},
> +
> +	[PCI_EXP_LNKCAP2 / 4] = {
> +		/* Link capabilities 2 register has reserved bits [30:25] and 0. */
> +		.ro = BIT(31) | GENMASK(24, 1),
> +	},
> +
> +	[PCI_EXP_LNKCTL2 / 4] = {
> +		/*
> +		 * Link control 2 register is RW.
> +		 *
> +		 * Link status 2 register has bits 5, 15 W1C;
> +		 * bits 10, 11 reserved and others are RO.
> +		 */
> +		.rw = GENMASK(15, 0),
> +		.w1c = (BIT(15) | BIT(5)) << 16,
> +		.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
> +	},
> +
> +	[PCI_EXP_SLTCAP2 / 4] = {
> +		/* Slot capabilities 2 register is reserved. */
> +	},
> +
> +	[PCI_EXP_SLTCTL2 / 4] = {
> +		/* Both Slot control 2 and Slot status 2 registers are reserved. */
> +	},
>  };
>  
>  /*
> -- 
> 2.32.0
> 

  reply	other threads:[~2021-11-29 16:46 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-31 18:12 [PATCH 0/7] PCI: aardvark controller fixes BATCH 3 Marek Behún
2021-10-31 18:12 ` [PATCH 1/7] PCI: pci-bridge-emul: Add description for class_revision field Marek Behún
2021-10-31 18:12 ` [PATCH 2/7] PCI: pci-bridge-emul: Add definitions for missing capabilities registers Marek Behún
2021-11-29 16:44   ` Lorenzo Pieralisi [this message]
2021-10-31 18:12 ` [PATCH 3/7] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2 registers on emulated bridge Marek Behún
2021-10-31 18:12 ` [PATCH 4/7] PCI: aardvark: Clear all MSIs at setup Marek Behún
2021-10-31 18:12 ` [PATCH 5/7] PCI: aardvark: Disable bus mastering and mask all interrupts when unbinding driver Marek Behún
2021-11-29 16:43   ` Lorenzo Pieralisi
2021-10-31 18:12 ` [PATCH 6/7] PCI: aardvark: Free config space for emulated root bridge when unbinding driver to fix memory leak Marek Behún
2021-10-31 18:12 ` [PATCH 7/7] PCI: aardvark: Reset PCIe card and disable PHY at driver unbind Marek Behún
2021-11-29 16:40   ` Lorenzo Pieralisi
2021-11-29 17:15     ` Marek Behún
2021-11-30 10:31       ` Lorenzo Pieralisi
2021-11-30 12:22         ` Marek Behún

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