From: Li Yang <leoyang.li@nxp.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Subject: [PATCH v2 2/4] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Date: Wed, 1 Dec 2021 18:46:34 -0600 [thread overview]
Message-ID: <20211202004636.5276-3-leoyang.li@nxp.com> (raw)
In-Reply-To: <20211202004636.5276-1-leoyang.li@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 215d2ee65c83..f1115fcd8088 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
"intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
- The second entry must be '0' or '1' based on physical PCIe controller index.
+ The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
--
2.25.1
next prev parent reply other threads:[~2021-12-02 0:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 0:46 [PATCH v2 0/4] layerscape-pci binding updates Li Yang
2021-12-02 0:46 ` [PATCH v2 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Li Yang
2021-12-02 0:46 ` Li Yang [this message]
2021-12-02 0:46 ` [PATCH v2 3/4] dt-bindings: pci: layerscape-pci: Add EP mode compatible strings for ls1028a Li Yang
2021-12-02 0:46 ` [PATCH v2 4/4] dt-bindings: pci: layerscape-pci: define AER/PME interrupts Li Yang
2021-12-13 19:18 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211202004636.5276-3-leoyang.li@nxp.com \
--to=leoyang.li@nxp.com \
--cc=Zhiqiang.Hou@nxp.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).