From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [PATCH v1 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
Date: Thu, 2 Dec 2021 17:17:17 +0300 [thread overview]
Message-ID: <20211202141726.1796793-2-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20211202141726.1796793-1-dmitry.baryshkov@linaro.org>
Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar
to the one used on SM8250. Add the compatible for SM8450.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 21 ++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index a0ae024c2d0c..73bc763c5009 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -15,6 +15,7 @@
- "qcom,pcie-sc8180x" for sc8180x
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
+ - "qcom,pcie-sm8450" for sm8450
- "qcom,pcie-ipq6018" for ipq6018
- reg:
@@ -169,6 +170,24 @@
- "ddrss_sf_tbu" PCIe SF TBU clock
- "pipe" PIPE clock
+- clock-names:
+ Usage: required for sm8450
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "aux" Auxiliary clock
+ - "cfg" Configuration clock
+ - "bus_master" Master AXI clock
+ - "bus_slave" Slave AXI clock
+ - "slave_q2a" Slave Q2A clock
+ - "tbu" PCIe TBU clock
+ - "ddrss_sf_tbu" PCIe SF TBU clock
+ - "pipe" PIPE clock
+ - "pipe_mux" PIPE MUX
+ - "phy_pipe" PIPE output clock
+ - "ref" REFERENCE clock
+ - "aggre0" Aggre NoC PCIe0 AXI clock
+ - "aggre1" Aggre NoC PCIe1 AXI clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -246,7 +265,7 @@
- "ahb" AHB reset
- reset-names:
- Usage: required for sc8180x, sdm845 and sm8250
+ Usage: required for sc8180x, sdm845, sm8250 and sm8450
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
--
2.33.0
next prev parent reply other threads:[~2021-12-02 14:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 14:17 [PATCH v1 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-02 14:17 ` Dmitry Baryshkov [this message]
2021-12-02 14:17 ` [PATCH v1 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
2021-12-07 14:26 ` Bjorn Andersson
2021-12-02 14:17 ` [PATCH v1 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
2021-12-07 14:30 ` Bjorn Andersson
2021-12-02 14:17 ` [PATCH v1 04/10] PCI: qcom: do not duplicate qcom_pcie_cfg fields in qcom_pcie struct Dmitry Baryshkov
2021-12-06 19:59 ` Bjorn Helgaas
2021-12-02 14:17 ` [PATCH v1 05/10] PCI: qcom: add flag to enable use of ddrss_sf_tbu clock Dmitry Baryshkov
2021-12-06 19:53 ` Bjorn Helgaas
2021-12-02 14:17 ` [PATCH v1 06/10] PCI: qcom: add support for SM8450 PCIe controllers Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 08/10] arm64: dts: qcom: sm8450: add PCIe0 root device Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Dmitry Baryshkov
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