From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: linux-pci@vger.kernel.org
Cc: tsbogend@alpha.franken.de, lorenzo.pieralisi@arm.com,
bhelgaas@google.com, linux@roeck-us.net,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 2/5] MIPS: ralink: implement 'pcibios_root_bridge_prepare()'
Date: Tue, 7 Dec 2021 11:49:21 +0100 [thread overview]
Message-ID: <20211207104924.21327-3-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20211207104924.21327-1-sergio.paracuellos@gmail.com>
PCI core code call 'pcibios_root_bridge_prepare()' function inside function
'pci_register_host_bridge()'. This point is very good way to properly enter
into this MIPS ralink specific code to properly setup I/O coherency units
with PCI memory addresses.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
arch/mips/ralink/mt7621.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index bd71f5b14238..d6efffd4dd20 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -10,6 +10,8 @@
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <linux/memblock.h>
+#include <linux/pci.h>
+#include <linux/bug.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
@@ -22,6 +24,35 @@
static void *detect_magic __initdata = detect_memory_region;
+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
+{
+ struct resource_entry *entry;
+ resource_size_t mask;
+
+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
+ if (!entry) {
+ pr_err("Cannot get memory resource\n");
+ return -EINVAL;
+ }
+
+ if (mips_cps_numiocu(0)) {
+ /*
+ * Hardware doesn't accept mask values with 1s after
+ * 0s (e.g. 0xffef), so warn if that's happen
+ */
+ mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
+ WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
+
+ write_gcr_reg1_base(entry->res->start);
+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
+ pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
+ (unsigned long long)read_gcr_reg1_base(),
+ (unsigned long long)read_gcr_reg1_mask());
+ }
+
+ return 0;
+}
+
phys_addr_t mips_cpc_default_phys_base(void)
{
panic("Cannot detect cpc address");
--
2.33.0
next prev parent reply other threads:[~2021-12-07 10:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-07 10:49 [PATCH v3 0/5] PCI: mt7621: Remove specific MIPS code from driver Sergio Paracuellos
2021-12-07 10:49 ` [PATCH v3 1/5] PCI: Let pcibios_root_bridge_prepare() access to 'bridge->windows' Sergio Paracuellos
2021-12-07 10:49 ` Sergio Paracuellos [this message]
2022-01-12 18:20 ` [PATCH v3 2/5] MIPS: ralink: implement 'pcibios_root_bridge_prepare()' Guenter Roeck
2022-01-12 20:10 ` Sergio Paracuellos
2022-01-12 20:10 ` Thomas Bogendoerfer
2022-01-13 5:53 ` Sergio Paracuellos
2021-12-07 10:49 ` [PATCH v3 3/5] PCI: mt7621: Avoid custom MIPS code in driver code Sergio Paracuellos
2021-12-07 10:49 ` [PATCH v3 4/5] PCI: mt7621: Add missing 'MODULE_LICENSE()' definition Sergio Paracuellos
2021-12-07 10:49 ` [PATCH v3 5/5] PCI: mt7621: Allow COMPILE_TEST for all arches Sergio Paracuellos
2022-01-12 14:42 ` [PATCH v3 0/5] PCI: mt7621: Remove specific MIPS code from driver Sergio Paracuellos
2022-01-12 18:06 ` Lorenzo Pieralisi
2022-01-12 18:21 ` Guenter Roeck
2022-01-12 20:09 ` Sergio Paracuellos
2022-01-12 21:52 ` Bjorn Helgaas
2022-01-13 5:52 ` Sergio Paracuellos
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