* [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform
@ 2021-12-11 2:17 Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
` (9 more replies)
0 siblings, 10 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
There are two different PCIe controllers and PHYs on SM8450, one having
one lane and another with two lanes. This set of patches adds support
for the first PCIe phy and controller only, support for the second PCIe
part will come later.
Changes since v2:
- Remove unnecessary comment in struct qcom_pcie_cfg
Changes since v1:
- Fix capitalization/wording of PCI patch subjects
- Add missing gen3x1 specification to PHY table names
----------------------------------------------------------------
Dmitry Baryshkov (10):
dt-bindings: pci: qcom: Document PCIe bindings for SM8450
dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings
phy: qcom-qmp: Add SM8450 PCIe0 PHY support
PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg
PCI: qcom: Add ddrss_sf_tbu flag
PCI: qcom: Add SM8450 PCIe support
arm64: dts: qcom: sm8450: add PCIe0 PHY node
arm64: dts: qcom: sm8450: add PCIe0 RC device
arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device
arm64: dts: qcom: sm8450-qrd: enable PCIe0 host
.../devicetree/bindings/pci/qcom,pcie.txt | 21 ++-
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 14 ++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 143 ++++++++++++++++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 88 ++++++++-----
drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 33 +++++
7 files changed, 388 insertions(+), 38 deletions(-)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
` (8 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy, Manivannan Sadhasivam
Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar
to the one used on SM8250. Add the compatible for SM8450.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 21 ++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index a0ae024c2d0c..73bc763c5009 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -15,6 +15,7 @@
- "qcom,pcie-sc8180x" for sc8180x
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
+ - "qcom,pcie-sm8450" for sm8450
- "qcom,pcie-ipq6018" for ipq6018
- reg:
@@ -169,6 +170,24 @@
- "ddrss_sf_tbu" PCIe SF TBU clock
- "pipe" PIPE clock
+- clock-names:
+ Usage: required for sm8450
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "aux" Auxiliary clock
+ - "cfg" Configuration clock
+ - "bus_master" Master AXI clock
+ - "bus_slave" Slave AXI clock
+ - "slave_q2a" Slave Q2A clock
+ - "tbu" PCIe TBU clock
+ - "ddrss_sf_tbu" PCIe SF TBU clock
+ - "pipe" PIPE clock
+ - "pipe_mux" PIPE MUX
+ - "phy_pipe" PIPE output clock
+ - "ref" REFERENCE clock
+ - "aggre0" Aggre NoC PCIe0 AXI clock
+ - "aggre1" Aggre NoC PCIe1 AXI clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -246,7 +265,7 @@
- "ahb" AHB reset
- reset-names:
- Usage: required for sc8180x, sdm845 and sm8250
+ Usage: required for sc8180x, sdm845, sm8250 and sm8450
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
There are two different PCIe PHYs on SM8450, one having one lane and
another with two lanes. Add DT bindings for the first one. Support for
second PCIe host and PHY will be submitted separately.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index c59bbca9a900..d18075cb2b5d 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -50,6 +50,7 @@ properties:
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-uni-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
- qcom,sm8450-qmp-ufs-phy
- qcom,sdx55-qmp-pcie-phy
- qcom,sdx55-qmp-usb3-uni-phy
@@ -333,6 +334,7 @@ allOf:
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
then:
properties:
clocks:
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-15 22:36 ` Bjorn Andersson
2021-12-11 2:17 ` [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
` (6 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
There are two different PCIe PHYs on SM8450, one having one lane (v5)
and another with two lanes (v5.20). This commit adds support for the
first PCIe phy only, support for the second PCIe PHY is coming in next
commits.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 33 ++++++++
2 files changed, 158 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index a959c97a699f..19c17678b999 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -2866,6 +2866,97 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
};
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
+};
+
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
+};
+
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
+};
+
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
+};
+
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+};
+
struct qmp_phy;
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -4116,6 +4207,37 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.is_dual_lane_phy = true,
};
+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 1,
+
+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
+ .clk_list = sdm845_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -5774,6 +5896,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sm8350-qmp-usb3-uni-phy",
.data = &sm8350_usb3_uniphy_cfg,
+ }, {
+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
}, {
.compatible = "qcom,sm8450-qmp-ufs-phy",
.data = &sm8450_ufsphy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index e15f461065bb..08422037f81b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -1069,6 +1069,15 @@
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
/* Only for QMP V5 PHY - QSERDES COM registers */
+#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
+#define QSERDES_V5_COM_SSC_PER1 0x01c
+#define QSERDES_V5_COM_SSC_PER2 0x020
+#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
+#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
+#define QSERDES_V5_COM_CLK_ENABLE1 0x048
+#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
#define QSERDES_V5_COM_PLL_IVCO 0x058
#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
@@ -1084,10 +1093,22 @@
#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
+#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
+#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
+#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
+#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
+#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
+#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
+#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
+#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
+#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
+#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
+#define QSERDES_V5_COM_CLK_SELECT 0x154
#define QSERDES_V5_COM_HSCLK_SEL 0x158
#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
+#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
@@ -1130,6 +1151,7 @@
#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
#define QSERDES_V5_RX_AC_JTAG_MODE 0x078
#define QSERDES_V5_RX_RX_TERM_BW 0x080
+#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V5_RX_GM_CAL 0x0dc
@@ -1167,6 +1189,17 @@
#define QSERDES_V5_RX_DCC_CTRL1 0x1a8
#define QSERDES_V5_RX_VTH_CODE 0x1b0
+/* Only for QMP V5 PHY - USB/PCIe PCS registers */
+#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
+
+/* Only for QMP V5 PHY - PCS_PCIE registers */
+#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
+
/* Only for QMP V5 PHY - UFS PCS registers */
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (2 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-13 23:24 ` Bjorn Helgaas
2021-12-11 2:17 ` [PATCH v3 05/10] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
` (5 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
In preparation to adding more flags to configuration data, use struct
qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating
all its fields. This would save us from the boilerplate code that just
copies flags values from one sruct to another one.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 39 +++++++++++---------------
1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1c3d1116bb60..51a0475173fb 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -204,8 +204,7 @@ struct qcom_pcie {
union qcom_pcie_resources res;
struct phy *phy;
struct gpio_desc *reset;
- const struct qcom_pcie_ops *ops;
- unsigned int pipe_clk_need_muxing:1;
+ const struct qcom_pcie_cfg *cfg;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -229,8 +228,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
struct qcom_pcie *pcie = to_qcom_pcie(pci);
/* Enable Link Training state machine */
- if (pcie->ops->ltssm_enable)
- pcie->ops->ltssm_enable(pcie);
+ if (pcie->cfg->ops->ltssm_enable)
+ pcie->cfg->ops->ltssm_enable(pcie);
return 0;
}
@@ -1176,7 +1175,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
- if (pcie->pipe_clk_need_muxing) {
+ if (pcie->cfg->pipe_clk_need_muxing) {
res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
if (IS_ERR(res->pipe_clk_src))
return PTR_ERR(res->pipe_clk_src);
@@ -1209,7 +1208,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
}
/* Set TCXO as clock source for pcie_pipe_clk_src */
- if (pcie->pipe_clk_need_muxing)
+ if (pcie->cfg->pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
@@ -1284,7 +1283,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
/* Set pipe clock as clock source for pcie_pipe_clk_src */
- if (pcie->pipe_clk_need_muxing)
+ if (pcie->cfg->pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
return clk_prepare_enable(res->pipe_clk);
@@ -1384,7 +1383,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_assert(pcie);
- ret = pcie->ops->init(pcie);
+ ret = pcie->cfg->ops->init(pcie);
if (ret)
return ret;
@@ -1392,16 +1391,16 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
if (ret)
goto err_deinit;
- if (pcie->ops->post_init) {
- ret = pcie->ops->post_init(pcie);
+ if (pcie->cfg->ops->post_init) {
+ ret = pcie->cfg->ops->post_init(pcie);
if (ret)
goto err_disable_phy;
}
qcom_ep_reset_deassert(pcie);
- if (pcie->ops->config_sid) {
- ret = pcie->ops->config_sid(pcie);
+ if (pcie->cfg->ops->config_sid) {
+ ret = pcie->cfg->ops->config_sid(pcie);
if (ret)
goto err;
}
@@ -1410,12 +1409,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
err:
qcom_ep_reset_assert(pcie);
- if (pcie->ops->post_deinit)
- pcie->ops->post_deinit(pcie);
+ if (pcie->cfg->ops->post_deinit)
+ pcie->cfg->ops->post_deinit(pcie);
err_disable_phy:
phy_power_off(pcie->phy);
err_deinit:
- pcie->ops->deinit(pcie);
+ pcie->cfg->ops->deinit(pcie);
return ret;
}
@@ -1531,7 +1530,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
struct pcie_port *pp;
struct dw_pcie *pci;
struct qcom_pcie *pcie;
- const struct qcom_pcie_cfg *pcie_cfg;
int ret;
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
@@ -1553,15 +1551,12 @@ static int qcom_pcie_probe(struct platform_device *pdev)
pcie->pci = pci;
- pcie_cfg = of_device_get_match_data(dev);
- if (!pcie_cfg || !pcie_cfg->ops) {
+ pcie->cfg = of_device_get_match_data(dev);
+ if (!pcie->cfg || !pcie->cfg->ops) {
dev_err(dev, "Invalid platform data\n");
return -EINVAL;
}
- pcie->ops = pcie_cfg->ops;
- pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing;
-
pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
if (IS_ERR(pcie->reset)) {
ret = PTR_ERR(pcie->reset);
@@ -1586,7 +1581,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}
- ret = pcie->ops->get_resources(pcie);
+ ret = pcie->cfg->ops->get_resources(pcie);
if (ret)
goto err_pm_runtime_put;
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 05/10] PCI: qcom: Add ddrss_sf_tbu flag
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (3 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 06/10] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
Qualcomm PCIe driver uses compatible string to check if the ddrss_sf_tbu
clock should be used. Since sc7280 support has added flags, switch to
the new mechanism to check if this clock should be used.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 51a0475173fb..2f9a9497733e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -195,6 +195,7 @@ struct qcom_pcie_ops {
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
unsigned int pipe_clk_need_muxing:1;
+ unsigned int has_ddrss_sf_tbu_clk:1;
};
struct qcom_pcie {
@@ -1164,7 +1165,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[3].id = "bus_slave";
res->clks[4].id = "slave_q2a";
res->clks[5].id = "tbu";
- if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) {
+ if (pcie->cfg->has_ddrss_sf_tbu_clk) {
res->clks[6].id = "ddrss_sf_tbu";
res->num_clks = 7;
} else {
@@ -1512,6 +1513,7 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
static const struct qcom_pcie_cfg sm8250_cfg = {
.ops = &ops_1_9_0,
+ .has_ddrss_sf_tbu_clk = true,
};
static const struct qcom_pcie_cfg sc7280_cfg = {
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 06/10] PCI: qcom: Add SM8450 PCIe support
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (4 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 05/10] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
` (3 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
On SM8450 platform PCIe hosts do not use all the clocks (and add several
additional clocks), so expand the driver to handle these requirements.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 47 +++++++++++++++++++-------
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2f9a9497733e..d129729bb2a6 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 {
/* 6 clocks typically, 7 for sm8250 */
struct qcom_pcie_resources_2_7_0 {
- struct clk_bulk_data clks[7];
+ struct clk_bulk_data clks[9];
int num_clks;
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
@@ -195,7 +195,10 @@ struct qcom_pcie_ops {
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
unsigned int pipe_clk_need_muxing:1;
+ unsigned int has_tbu_clk:1;
unsigned int has_ddrss_sf_tbu_clk:1;
+ unsigned int has_aggre0_clk:1;
+ unsigned int has_aggre1_clk:1;
};
struct qcom_pcie {
@@ -1146,6 +1149,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ unsigned int idx;
int ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
@@ -1159,18 +1163,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret)
return ret;
- res->clks[0].id = "aux";
- res->clks[1].id = "cfg";
- res->clks[2].id = "bus_master";
- res->clks[3].id = "bus_slave";
- res->clks[4].id = "slave_q2a";
- res->clks[5].id = "tbu";
- if (pcie->cfg->has_ddrss_sf_tbu_clk) {
- res->clks[6].id = "ddrss_sf_tbu";
- res->num_clks = 7;
- } else {
- res->num_clks = 6;
- }
+ idx = 0;
+ res->clks[idx++].id = "aux";
+ res->clks[idx++].id = "cfg";
+ res->clks[idx++].id = "bus_master";
+ res->clks[idx++].id = "bus_slave";
+ res->clks[idx++].id = "slave_q2a";
+ if (pcie->cfg->has_tbu_clk)
+ res->clks[idx++].id = "tbu";
+ if (pcie->cfg->has_ddrss_sf_tbu_clk)
+ res->clks[idx++].id = "ddrss_sf_tbu";
+ if (pcie->cfg->has_aggre0_clk)
+ res->clks[idx++].id = "aggre0";
+ if (pcie->cfg->has_aggre1_clk)
+ res->clks[idx++].id = "aggre1";
+
+ res->num_clks = idx;
ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
if (ret < 0)
@@ -1509,15 +1517,27 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
static const struct qcom_pcie_cfg sdm845_cfg = {
.ops = &ops_2_7_0,
+ .has_tbu_clk = true,
};
static const struct qcom_pcie_cfg sm8250_cfg = {
.ops = &ops_1_9_0,
+ .has_tbu_clk = true,
.has_ddrss_sf_tbu_clk = true,
};
+/* Only for the PCIe0! */
+static const struct qcom_pcie_cfg sm8450_cfg = {
+ .ops = &ops_1_9_0,
+ .has_ddrss_sf_tbu_clk = true,
+ .pipe_clk_need_muxing = true,
+ .has_aggre0_clk = true,
+ .has_aggre1_clk = true,
+};
+
static const struct qcom_pcie_cfg sc7280_cfg = {
.ops = &ops_1_9_0,
+ .has_tbu_clk = true,
.pipe_clk_need_muxing = true,
};
@@ -1625,6 +1645,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
+ { .compatible = "qcom,pcie-sm8450", .data = &sm8450_cfg },
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
{ }
};
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (5 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 06/10] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
Add device tree node for the first PCIe PHY device found on the Qualcomm
SM8450 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 16a789cacb65..a047d8a22897 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -558,8 +558,12 @@ gcc: clock-controller@100000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- clock-names = "bi_tcxo", "sleep_clk";
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&pcie0_lane>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo",
+ "pcie_0_pipe_clk",
+ "sleep_clk";
};
qupv3_id_0: geniqup@9c0000 {
@@ -625,6 +629,40 @@ i2c14: i2c@a98000 {
};
};
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
+ reg = <0 0x01c06000 0 0x200>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+
+ pcie0_lane: lanes@1c06200 {
+ reg = <0 0x1c06e00 0 0x200>, /* tx */
+ <0 0x1c07000 0 0x200>, /* rx */
+ <0 0x1c06200 0 0x200>, /* pcs */
+ <0 0x1c06600 0 0x200>; /* pcs_pcie */
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+ };
+ };
+
config_noc: interconnect@1500000 {
compatible = "qcom,sm8450-config-noc";
reg = <0 0x01500000 0 0x1c000>;
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (6 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-15 22:35 ` Bjorn Andersson
2021-12-11 2:17 ` [PATCH v3 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Dmitry Baryshkov
9 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy, Manivannan Sadhasivam
Add device tree node for the first PCIe host found on the Qualcomm
SM8450 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 101 +++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index a047d8a22897..09087a34a007 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -627,6 +627,84 @@ i2c14: i2c@a98000 {
#size-cells = <0>;
status = "disabled";
};
+ ];
+
+ pcie0: pci@1c00000 {
+ compatible = "qcom,pcie-sm8450";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+ <&pcie0_lane>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ iommus = <&apps_smmu 0x1c00 0x7f>;
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+ power-domain-names = "gdsc";
+
+ phys = <&pcie0_lane>;
+ phy-names = "pciephy";
+
+ perst-gpio = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "pci";
+
+ status = "disabled";
};
pcie0_phy: phy@1c06000 {
@@ -763,6 +841,29 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 211>;
wakeup-parent = <&pdc>;
+ pcie0_default_state: pcie0-default {
+ perst {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio95";
+ function = "pcie0_clkreqn";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio96";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup_i2c13_default_state: qup-i2c13-default-state {
mux {
pins = "gpio48", "gpio49";
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (7 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Dmitry Baryshkov
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
Enable PCIe0 PHY on the SM8450 QRD device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index cd74b97b9018..e02d3c86e365 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -346,10 +346,20 @@ vreg_l6e_1p2: ldo6 {
};
};
+&pcie0_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l5b_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
&qupv3_id_0 {
status = "okay";
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <28 4>, <36 4>;
};
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
` (8 preceding siblings ...)
2021-12-11 2:17 ` [PATCH v3 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Dmitry Baryshkov
@ 2021-12-11 2:17 ` Dmitry Baryshkov
9 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-11 2:17 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi
Cc: Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
Enable PCIe0 host on SM8450 QRD device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index e02d3c86e365..f6577ca7d2df 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -346,6 +346,10 @@ vreg_l6e_1p2: ldo6 {
};
};
+&pcie0 {
+ status = "okay";
+};
+
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
--
2.33.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg
2021-12-11 2:17 ` [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
@ 2021-12-13 23:24 ` Bjorn Helgaas
0 siblings, 0 replies; 17+ messages in thread
From: Bjorn Helgaas @ 2021-12-13 23:24 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Vinod Koul,
Kishon Vijay Abraham I, Stanimir Varbanov, Lorenzo Pieralisi,
Bjorn Helgaas, Krzysztof Wilczyński, linux-arm-msm,
linux-pci, devicetree, linux-phy
On Sat, Dec 11, 2021 at 05:17:52AM +0300, Dmitry Baryshkov wrote:
> In preparation to adding more flags to configuration data, use struct
> qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating
> all its fields. This would save us from the boilerplate code that just
> copies flags values from one sruct to another one.
s/flags values/flag values/
s/sruct/struct/
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device
2021-12-11 2:17 ` [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
@ 2021-12-15 22:35 ` Bjorn Andersson
2021-12-17 1:22 ` Dmitry Baryshkov
0 siblings, 1 reply; 17+ messages in thread
From: Bjorn Andersson @ 2021-12-15 22:35 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Rob Herring, Vinod Koul, Kishon Vijay Abraham I,
Stanimir Varbanov, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczy??ski, linux-arm-msm, linux-pci, devicetree,
linux-phy, Manivannan Sadhasivam
On Fri 10 Dec 20:17 CST 2021, Dmitry Baryshkov wrote:
> Add device tree node for the first PCIe host found on the Qualcomm
> SM8450 platform.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 101 +++++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index a047d8a22897..09087a34a007 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -627,6 +627,84 @@ i2c14: i2c@a98000 {
> #size-cells = <0>;
> status = "disabled";
> };
> + ];
> +
> + pcie0: pci@1c00000 {
> + compatible = "qcom,pcie-sm8450";
> + reg = <0 0x01c00000 0 0x3000>,
> + <0 0x60000000 0 0xf1d>,
> + <0 0x60000f20 0 0xa8>,
> + <0 0x60001000 0 0x1000>,
> + <0 0x60100000 0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
You need to pad these with a couple more zeros, see 0ac10b291bee
("arm64: dts: qcom: Fix 'interrupt-map' parent address cells")
> +
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
> + <&pcie0_lane>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
> + clock-names = "pipe",
> + "pipe_mux",
> + "phy_pipe",
> + "ref",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "aggre0",
> + "aggre1";
> +
> + iommus = <&apps_smmu 0x1c00 0x7f>;
> + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
> + <0x100 &apps_smmu 0x1c01 0x1>;
> +
> + resets = <&gcc GCC_PCIE_0_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_0_GDSC>;
> + power-domain-names = "gdsc";
> +
> + phys = <&pcie0_lane>;
> + phy-names = "pciephy";
> +
> + perst-gpio = <&tlmm 94 GPIO_ACTIVE_LOW>;
> + enable-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_default_state>;
> +
> + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
> + interconnect-names = "pci";
> +
> + status = "disabled";
> };
>
> pcie0_phy: phy@1c06000 {
> @@ -763,6 +841,29 @@ tlmm: pinctrl@f100000 {
> gpio-ranges = <&tlmm 0 0 211>;
> wakeup-parent = <&pdc>;
>
> + pcie0_default_state: pcie0-default {
Binding states that the node name needs to have the suffix "-state".
Regards,
Bjorn
> + perst {
> + pins = "gpio94";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq {
> + pins = "gpio95";
> + function = "pcie0_clkreqn";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake {
> + pins = "gpio96";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> qup_i2c13_default_state: qup-i2c13-default-state {
> mux {
> pins = "gpio48", "gpio49";
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support
2021-12-11 2:17 ` [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
@ 2021-12-15 22:36 ` Bjorn Andersson
2021-12-16 1:28 ` Dmitry Baryshkov
0 siblings, 1 reply; 17+ messages in thread
From: Bjorn Andersson @ 2021-12-15 22:36 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Rob Herring, Vinod Koul, Kishon Vijay Abraham I,
Stanimir Varbanov, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczy??ski, linux-arm-msm, linux-pci, devicetree,
linux-phy
On Fri 10 Dec 20:17 CST 2021, Dmitry Baryshkov wrote:
> There are two different PCIe PHYs on SM8450, one having one lane (v5)
> and another with two lanes (v5.20). This commit adds support for the
> first PCIe phy only, support for the second PCIe PHY is coming in next
> commits.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Note that this is going to be merged separately from the PCIe controller
patches, sending them in separate series would make that clearer to the
maintainers.
Regards,
Bjorn
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qmp.h | 33 ++++++++
> 2 files changed, 158 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index a959c97a699f..19c17678b999 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -2866,6 +2866,97 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> };
>
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> struct qmp_phy;
>
> /* struct qmp_phy_cfg - per-PHY initialization config */
> @@ -4116,6 +4207,37 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .is_dual_lane_phy = true,
> };
>
> +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = SERDES_START | PCS_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> .type = PHY_TYPE_USB3,
> .nlanes = 1,
> @@ -5774,6 +5896,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> }, {
> .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> .data = &sm8350_usb3_uniphy_cfg,
> + }, {
> + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> }, {
> .compatible = "qcom,sm8450-qmp-ufs-phy",
> .data = &sm8450_ufsphy_cfg,
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index e15f461065bb..08422037f81b 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -1069,6 +1069,15 @@
> #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
>
> /* Only for QMP V5 PHY - QSERDES COM registers */
> +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
> +#define QSERDES_V5_COM_SSC_PER1 0x01c
> +#define QSERDES_V5_COM_SSC_PER2 0x020
> +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
> +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
> +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
> +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
> +#define QSERDES_V5_COM_CLK_ENABLE1 0x048
> +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
> #define QSERDES_V5_COM_PLL_IVCO 0x058
> #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
> #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
> @@ -1084,10 +1093,22 @@
> #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
> #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
> #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
> +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
> +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
> +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
> +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
> +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
> +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
> #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
> +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
> +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
> +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
> +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
> #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
> +#define QSERDES_V5_COM_CLK_SELECT 0x154
> #define QSERDES_V5_COM_HSCLK_SEL 0x158
> #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
> +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
> #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> @@ -1130,6 +1151,7 @@
> #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
> #define QSERDES_V5_RX_AC_JTAG_MODE 0x078
> #define QSERDES_V5_RX_RX_TERM_BW 0x080
> +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
> #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
> #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
> #define QSERDES_V5_RX_GM_CAL 0x0dc
> @@ -1167,6 +1189,17 @@
> #define QSERDES_V5_RX_DCC_CTRL1 0x1a8
> #define QSERDES_V5_RX_VTH_CODE 0x1b0
>
> +/* Only for QMP V5 PHY - USB/PCIe PCS registers */
> +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
> +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> +
> +/* Only for QMP V5 PHY - PCS_PCIE registers */
> +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
> +
> /* Only for QMP V5 PHY - UFS PCS registers */
> #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
> #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support
2021-12-15 22:36 ` Bjorn Andersson
@ 2021-12-16 1:28 ` Dmitry Baryshkov
2021-12-18 5:17 ` Vinod Koul
0 siblings, 1 reply; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-16 1:28 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Vinod Koul, Kishon Vijay Abraham I,
Stanimir Varbanov, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczy??ski, linux-arm-msm, linux-pci, devicetree,
linux-phy
On Thu, 16 Dec 2021 at 01:37, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> On Fri 10 Dec 20:17 CST 2021, Dmitry Baryshkov wrote:
>
> > There are two different PCIe PHYs on SM8450, one having one lane (v5)
> > and another with two lanes (v5.20). This commit adds support for the
> > first PCIe phy only, support for the second PCIe PHY is coming in next
> > commits.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>
> Note that this is going to be merged separately from the PCIe controller
> patches, sending them in separate series would make that clearer to the
> maintainers.
Hmm. If you think it would be better, I can split it into 3 series:
- PCIe RC
- PCIe PHY
- dts changes
Does that make sense?
>
> Regards,
> Bjorn
>
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++++++++++++
> > drivers/phy/qualcomm/phy-qcom-qmp.h | 33 ++++++++
> > 2 files changed, 158 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > index a959c97a699f..19c17678b999 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > @@ -2866,6 +2866,97 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> > QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> > +};
> > +
> > struct qmp_phy;
> >
> > /* struct qmp_phy_cfg - per-PHY initialization config */
> > @@ -4116,6 +4207,37 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> > .is_dual_lane_phy = true,
> > };
> >
> > +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> > + .type = PHY_TYPE_PCIE,
> > + .nlanes = 1,
> > +
> > + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> > + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> > + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> > + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> > + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> > + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> > + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> > + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> > + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> > + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> > + .clk_list = sdm845_pciephy_clk_l,
> > + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> > + .reset_list = sdm845_pciephy_reset_l,
> > + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> > + .vreg_list = qmp_phy_vreg_l,
> > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > + .regs = sm8250_pcie_regs_layout,
> > +
> > + .start_ctrl = SERDES_START | PCS_START,
> > + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> > + .phy_status = PHYSTATUS,
> > +
> > + .has_pwrdn_delay = true,
> > + .pwrdn_delay_min = 995, /* us */
> > + .pwrdn_delay_max = 1005, /* us */
> > +};
> > +
> > static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> > .type = PHY_TYPE_USB3,
> > .nlanes = 1,
> > @@ -5774,6 +5896,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> > }, {
> > .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> > .data = &sm8350_usb3_uniphy_cfg,
> > + }, {
> > + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> > + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> > }, {
> > .compatible = "qcom,sm8450-qmp-ufs-phy",
> > .data = &sm8450_ufsphy_cfg,
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> > index e15f461065bb..08422037f81b 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> > @@ -1069,6 +1069,15 @@
> > #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
> >
> > /* Only for QMP V5 PHY - QSERDES COM registers */
> > +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
> > +#define QSERDES_V5_COM_SSC_PER1 0x01c
> > +#define QSERDES_V5_COM_SSC_PER2 0x020
> > +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
> > +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
> > +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
> > +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
> > +#define QSERDES_V5_COM_CLK_ENABLE1 0x048
> > +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
> > #define QSERDES_V5_COM_PLL_IVCO 0x058
> > #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
> > #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
> > @@ -1084,10 +1093,22 @@
> > #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
> > #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
> > #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
> > +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
> > +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
> > +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
> > +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
> > +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
> > +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
> > #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
> > +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
> > +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
> > +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
> > +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
> > #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
> > +#define QSERDES_V5_COM_CLK_SELECT 0x154
> > #define QSERDES_V5_COM_HSCLK_SEL 0x158
> > #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
> > +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
> > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> > @@ -1130,6 +1151,7 @@
> > #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
> > #define QSERDES_V5_RX_AC_JTAG_MODE 0x078
> > #define QSERDES_V5_RX_RX_TERM_BW 0x080
> > +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
> > #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
> > #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
> > #define QSERDES_V5_RX_GM_CAL 0x0dc
> > @@ -1167,6 +1189,17 @@
> > #define QSERDES_V5_RX_DCC_CTRL1 0x1a8
> > #define QSERDES_V5_RX_VTH_CODE 0x1b0
> >
> > +/* Only for QMP V5 PHY - USB/PCIe PCS registers */
> > +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
> > +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> > +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> > +
> > +/* Only for QMP V5 PHY - PCS_PCIE registers */
> > +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> > +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> > +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
> > +
> > /* Only for QMP V5 PHY - UFS PCS registers */
> > #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
> > #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
> > --
> > 2.33.0
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device
2021-12-15 22:35 ` Bjorn Andersson
@ 2021-12-17 1:22 ` Dmitry Baryshkov
0 siblings, 0 replies; 17+ messages in thread
From: Dmitry Baryshkov @ 2021-12-17 1:22 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Vinod Koul, Kishon Vijay Abraham I,
Stanimir Varbanov, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczy??ski, linux-arm-msm, linux-pci, devicetree,
linux-phy, Manivannan Sadhasivam
On 16/12/2021 01:35, Bjorn Andersson wrote:
> On Fri 10 Dec 20:17 CST 2021, Dmitry Baryshkov wrote:
>
>> Add device tree node for the first PCIe host found on the Qualcomm
>> SM8450 platform.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 101 +++++++++++++++++++++++++++
>> 1 file changed, 101 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index a047d8a22897..09087a34a007 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -627,6 +627,84 @@ i2c14: i2c@a98000 {
>> #size-cells = <0>;
>> status = "disabled";
>> };
>> + ];
>> +
>> + pcie0: pci@1c00000 {
>> + compatible = "qcom,pcie-sm8450";
>> + reg = <0 0x01c00000 0 0x3000>,
>> + <0 0x60000000 0 0xf1d>,
>> + <0 0x60000f20 0 0xa8>,
>> + <0 0x60001000 0 0x1000>,
>> + <0 0x60100000 0 0x100000>;
>> + reg-names = "parf", "dbi", "elbi", "atu", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <0>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
>> + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
>> +
>> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "msi";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>
> You need to pad these with a couple more zeros, see 0ac10b291bee
> ("arm64: dts: qcom: Fix 'interrupt-map' parent address cells")
Not quite. sm8450 does not define its (yet), so GICv3 node does not
define address/size cells.
>
>> +
>> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
>> + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
>> + <&pcie0_lane>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
>> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
>> + clock-names = "pipe",
>> + "pipe_mux",
>> + "phy_pipe",
>> + "ref",
>> + "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a",
>> + "ddrss_sf_tbu",
>> + "aggre0",
>> + "aggre1";
>> +
>> + iommus = <&apps_smmu 0x1c00 0x7f>;
>> + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
>> + <0x100 &apps_smmu 0x1c01 0x1>;
>> +
>> + resets = <&gcc GCC_PCIE_0_BCR>;
>> + reset-names = "pci";
>> +
>> + power-domains = <&gcc PCIE_0_GDSC>;
>> + power-domain-names = "gdsc";
>> +
>> + phys = <&pcie0_lane>;
>> + phy-names = "pciephy";
>> +
>> + perst-gpio = <&tlmm 94 GPIO_ACTIVE_LOW>;
>> + enable-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pcie0_default_state>;
>> +
>> + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
>> + interconnect-names = "pci";
>> +
>> + status = "disabled";
>> };
>>
>> pcie0_phy: phy@1c06000 {
>> @@ -763,6 +841,29 @@ tlmm: pinctrl@f100000 {
>> gpio-ranges = <&tlmm 0 0 211>;
>> wakeup-parent = <&pdc>;
>>
>> + pcie0_default_state: pcie0-default {
>
> Binding states that the node name needs to have the suffix "-state".
>
> Regards,
> Bjorn
>
>> + perst {
>> + pins = "gpio94";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + clkreq {
>> + pins = "gpio95";
>> + function = "pcie0_clkreqn";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + wake {
>> + pins = "gpio96";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> qup_i2c13_default_state: qup-i2c13-default-state {
>> mux {
>> pins = "gpio48", "gpio49";
>> --
>> 2.33.0
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support
2021-12-16 1:28 ` Dmitry Baryshkov
@ 2021-12-18 5:17 ` Vinod Koul
0 siblings, 0 replies; 17+ messages in thread
From: Vinod Koul @ 2021-12-18 5:17 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Andy Gross, Rob Herring, Kishon Vijay Abraham I,
Stanimir Varbanov, Lorenzo Pieralisi, Bjorn Helgaas,
Krzysztof Wilczy??ski, linux-arm-msm, linux-pci, devicetree,
linux-phy
On 16-12-21, 04:28, Dmitry Baryshkov wrote:
> On Thu, 16 Dec 2021 at 01:37, Bjorn Andersson
> <bjorn.andersson@linaro.org> wrote:
> >
> > On Fri 10 Dec 20:17 CST 2021, Dmitry Baryshkov wrote:
> >
> > > There are two different PCIe PHYs on SM8450, one having one lane (v5)
> > > and another with two lanes (v5.20). This commit adds support for the
> > > first PCIe phy only, support for the second PCIe PHY is coming in next
> > > commits.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> >
> > Note that this is going to be merged separately from the PCIe controller
> > patches, sending them in separate series would make that clearer to the
> > maintainers.
>
> Hmm. If you think it would be better, I can split it into 3 series:
> - PCIe RC
> - PCIe PHY
> - dts changes
>
> Does that make sense?
Yes it is a very good practice if the are not dependent. Unfortunately
many people just send the whole pile... once phy and pcie patches are
merged you should send dts for merge
>
> >
> > Regards,
> > Bjorn
> >
> > > ---
> > > drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++++++++++++
> > > drivers/phy/qualcomm/phy-qcom-qmp.h | 33 ++++++++
> > > 2 files changed, 158 insertions(+)
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > > index a959c97a699f..19c17678b999 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > > @@ -2866,6 +2866,97 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
> > > QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
> > > + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
> > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> > > +};
> > > +
> > > struct qmp_phy;
> > >
> > > /* struct qmp_phy_cfg - per-PHY initialization config */
> > > @@ -4116,6 +4207,37 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> > > .is_dual_lane_phy = true,
> > > };
> > >
> > > +static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
> > > + .type = PHY_TYPE_PCIE,
> > > + .nlanes = 1,
> > > +
> > > + .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
> > > + .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
> > > + .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
> > > + .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
> > > + .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
> > > + .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
> > > + .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
> > > + .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
> > > + .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
> > > + .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
> > > + .clk_list = sdm845_pciephy_clk_l,
> > > + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> > > + .reset_list = sdm845_pciephy_reset_l,
> > > + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> > > + .vreg_list = qmp_phy_vreg_l,
> > > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > > + .regs = sm8250_pcie_regs_layout,
> > > +
> > > + .start_ctrl = SERDES_START | PCS_START,
> > > + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> > > + .phy_status = PHYSTATUS,
> > > +
> > > + .has_pwrdn_delay = true,
> > > + .pwrdn_delay_min = 995, /* us */
> > > + .pwrdn_delay_max = 1005, /* us */
> > > +};
> > > +
> > > static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> > > .type = PHY_TYPE_USB3,
> > > .nlanes = 1,
> > > @@ -5774,6 +5896,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> > > }, {
> > > .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
> > > .data = &sm8350_usb3_uniphy_cfg,
> > > + }, {
> > > + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
> > > + .data = &sm8450_qmp_gen3x1_pciephy_cfg,
> > > }, {
> > > .compatible = "qcom,sm8450-qmp-ufs-phy",
> > > .data = &sm8450_ufsphy_cfg,
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> > > index e15f461065bb..08422037f81b 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> > > @@ -1069,6 +1069,15 @@
> > > #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
> > >
> > > /* Only for QMP V5 PHY - QSERDES COM registers */
> > > +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010
> > > +#define QSERDES_V5_COM_SSC_PER1 0x01c
> > > +#define QSERDES_V5_COM_SSC_PER2 0x020
> > > +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
> > > +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028
> > > +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030
> > > +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034
> > > +#define QSERDES_V5_COM_CLK_ENABLE1 0x048
> > > +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050
> > > #define QSERDES_V5_COM_PLL_IVCO 0x058
> > > #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
> > > #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
> > > @@ -1084,10 +1093,22 @@
> > > #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
> > > #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
> > > #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
> > > +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc
> > > +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0
> > > +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4
> > > +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8
> > > +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc
> > > +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0
> > > #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
> > > +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110
> > > +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114
> > > +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118
> > > +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c
> > > #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
> > > +#define QSERDES_V5_COM_CLK_SELECT 0x154
> > > #define QSERDES_V5_COM_HSCLK_SEL 0x158
> > > #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
> > > +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c
> > > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
> > > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
> > > #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
> > > @@ -1130,6 +1151,7 @@
> > > #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
> > > #define QSERDES_V5_RX_AC_JTAG_MODE 0x078
> > > #define QSERDES_V5_RX_RX_TERM_BW 0x080
> > > +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc
> > > #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
> > > #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
> > > #define QSERDES_V5_RX_GM_CAL 0x0dc
> > > @@ -1167,6 +1189,17 @@
> > > #define QSERDES_V5_RX_DCC_CTRL1 0x1a8
> > > #define QSERDES_V5_RX_VTH_CODE 0x1b0
> > >
> > > +/* Only for QMP V5 PHY - USB/PCIe PCS registers */
> > > +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
> > > +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> > > +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> > > +
> > > +/* Only for QMP V5 PHY - PCS_PCIE registers */
> > > +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> > > +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> > > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> > > +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
> > > +
> > > /* Only for QMP V5 PHY - UFS PCS registers */
> > > #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
> > > #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
> > > --
> > > 2.33.0
> > >
>
>
>
> --
> With best wishes
> Dmitry
--
~Vinod
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2021-12-18 5:17 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-11 2:17 [PATCH v3 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
2021-12-15 22:36 ` Bjorn Andersson
2021-12-16 1:28 ` Dmitry Baryshkov
2021-12-18 5:17 ` Vinod Koul
2021-12-11 2:17 ` [PATCH v3 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
2021-12-13 23:24 ` Bjorn Helgaas
2021-12-11 2:17 ` [PATCH v3 05/10] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 06/10] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
2021-12-15 22:35 ` Bjorn Andersson
2021-12-17 1:22 ` Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Dmitry Baryshkov
2021-12-11 2:17 ` [PATCH v3 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Dmitry Baryshkov
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