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From: Bjorn Helgaas <helgaas@kernel.org>
To: Lukas Wunner <lukas@wunner.de>
Cc: linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Subject: [PATCH] PCI: pciehp: Simplify Command Completion checking
Date: Thu, 10 Feb 2022 17:38:06 -0600	[thread overview]
Message-ID: <20220210233806.663609-1-helgaas@kernel.org> (raw)

From: Bjorn Helgaas <bhelgaas@google.com>

If a device sets the No Command Completed Support bit in the Slot
Capabilities register (PCIe r6.0, sec 7.5.3.9), it does not generate
software notifications when a command is completed, and software can
write all fields of the Slot Control register without any delays.

Since we only need to wait for command completion on devices that do *not*
set the No Command Completed Support bit, there's no need to even set the
ctrl->cmd_busy bit that tracks when the device is busy handling a command.

Set the ctrl->cmd_busy bit only when we need to wait for a command to
complete.  This shouldn't make much functional difference, but does avoid
an smp_mb() for controllers that set PCI_EXP_SLTCAP_NCCS.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 drivers/pci/hotplug/pciehp_hpc.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 1c1ebf3dad43..0ff928693a13 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -114,13 +114,6 @@ static void pcie_wait_cmd(struct controller *ctrl)
 	unsigned long now, timeout;
 	int rc;
 
-	/*
-	 * If the controller does not generate notifications for command
-	 * completions, we never need to wait between writes.
-	 */
-	if (NO_CMD_CMPL(ctrl))
-		return;
-
 	if (!ctrl->cmd_busy)
 		return;
 
@@ -173,8 +166,17 @@ static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 	slot_ctrl_orig = slot_ctrl;
 	slot_ctrl &= ~mask;
 	slot_ctrl |= (cmd & mask);
-	ctrl->cmd_busy = 1;
-	smp_mb();
+
+	/*
+	 * If controller generates Command Completed events, we must wait
+	 * for it to finish one command before sending another, so we need
+	 * to keep track of when the controller is busy.
+	 */
+	if (!NO_CMD_CMPL(ctrl)) {
+		ctrl->cmd_busy = 1;
+		smp_mb();
+	}
+
 	ctrl->slot_ctrl = slot_ctrl;
 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 	ctrl->cmd_started = jiffies;
-- 
2.25.1


             reply	other threads:[~2022-02-10 23:38 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-10 23:38 Bjorn Helgaas [this message]
2022-05-08 13:36 ` [PATCH] PCI: pciehp: Simplify Command Completion checking Lukas Wunner

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