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Sun, 20 Feb 2022 01:58:15 -0800 From: Yishai Hadas To: , , , CC: , , , , , , , , , , , , Subject: [PATCH V8 mlx5-next 01/15] PCI/IOV: Add pci_iov_vf_id() to get VF index Date: Sun, 20 Feb 2022 11:57:02 +0200 Message-ID: <20220220095716.153757-2-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220220095716.153757-1-yishaih@nvidia.com> References: <20220220095716.153757-1-yishaih@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4ae68a07-f3dc-48d8-e02c-08d9f4578769 X-MS-TrafficTypeDiagnostic: DM4PR12MB5229:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HMnC4A6MmR9E4ejrhLpRTS6yqOs5aIj0FvZ7GzRVNo8EeR1JOYWcYUD27QuQI6MClumU+9caSzWyiP/6/4CBBb3ah+Z9708LujRX+EOH33kQ2/Xq6QwSAwL37LwPj3j6GWL+bSiMnKzPw0NfEZUZgF5rj7FGQohc/WM1l9Aoa+xI4Igi1cj0XrMDZLcR5T2++C/TQzqzI5Ryh7T7ifhsD3gwjgWdSdXNcK1PC3uJalxvJBC599SR9zzidssMu72namGiUP6e49FVhDQC9E4vm+oreIs4Z1n2VzLMA34gbK1uWzvvCBmxLKJvvQkohTAR+dpQBA7GdrsT1gb1bwDWg3r7ys1Exl/XWwOfm03dMZm39qdhZ71UxeG+2pQw6UYZRyXaDpn+IYJe2clPGi1kY+ItYJxXWFrhvn8Wab8MJt2+IJiNJI5Lt4uGkGD8BuL4buTapzN2HRVyVKk2YwVOr4RrnIiIYsw/y9PM4BPbjxpaNbGBMYjN5AJ1NmATP9ni+vFP4d3My+fhahM5SD6p75PqxUgk1P4GQX79PJ7H6LRrnhj+NxMb4cBvUYP0IgjmDhJpPh/8bzHe+kij8YAW2zQHwqYlHaUsrYQKC+siSQDQGwdhlYS0mM2A5QrLvXNj68Pgqa0UhtGER7uzrqXKyrSfI9Ee7DGSgdVHBhGjuRMdByZvbzbijnM14vort/GwQ3PQxo6ento50y59lUH/ew== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(26005)(47076005)(186003)(83380400001)(426003)(336012)(81166007)(356005)(4326008)(36860700001)(8676002)(1076003)(8936002)(7416002)(5660300002)(70206006)(2906002)(70586007)(6666004)(7696005)(2616005)(6636002)(54906003)(110136005)(316002)(508600001)(86362001)(40460700003)(36756003)(82310400004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2022 09:58:21.9580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ae68a07-f3dc-48d8-e02c-08d9f4578769 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5229 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jason Gunthorpe The PCI core uses the VF index internally, often called the vf_id, during the setup of the VF, eg pci_iov_add_virtfn(). This index is needed for device drivers that implement live migration for their internal operations that configure/control their VFs. Specifically, mlx5_vfio_pci driver that is introduced in coming patches from this series needs it and not the bus/device/function which is exposed today. Add pci_iov_vf_id() which computes the vf_id by reversing the math that was used to create the bus/device/function. Signed-off-by: Jason Gunthorpe Acked-by: Bjorn Helgaas Signed-off-by: Leon Romanovsky Signed-off-by: Yishai Hadas --- drivers/pci/iov.c | 14 ++++++++++++++ include/linux/pci.h | 8 +++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 0267977c9f17..2e9f3d70803a 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -33,6 +33,20 @@ int pci_iov_virtfn_devfn(struct pci_dev *dev, int vf_id) } EXPORT_SYMBOL_GPL(pci_iov_virtfn_devfn); +int pci_iov_vf_id(struct pci_dev *dev) +{ + struct pci_dev *pf; + + if (!dev->is_virtfn) + return -EINVAL; + + pf = pci_physfn(dev); + return (((dev->bus->number << 8) + dev->devfn) - + ((pf->bus->number << 8) + pf->devfn + pf->sriov->offset)) / + pf->sriov->stride; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_id); + /* * Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may * change when NumVFs changes. diff --git a/include/linux/pci.h b/include/linux/pci.h index 8253a5413d7c..3d4ff7b35ad1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2166,7 +2166,7 @@ void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); #ifdef CONFIG_PCI_IOV int pci_iov_virtfn_bus(struct pci_dev *dev, int id); int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); - +int pci_iov_vf_id(struct pci_dev *dev); int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); void pci_disable_sriov(struct pci_dev *dev); @@ -2194,6 +2194,12 @@ static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) { return -ENOSYS; } + +static inline int pci_iov_vf_id(struct pci_dev *dev) +{ + return -ENOSYS; +} + static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) { return -ENODEV; } -- 2.18.1