From: "Pali Rohár" <pali@kernel.org>
To: "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Marek Behún" <kabel@kernel.org>,
"Russell King" <rmk+kernel@armlinux.org.uk>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 10/12] PCI: mvebu: Fix macro names and comments about legacy interrupts
Date: Tue, 22 Feb 2022 16:50:28 +0100 [thread overview]
Message-ID: <20220222155030.988-11-pali@kernel.org> (raw)
In-Reply-To: <20220222155030.988-1-pali@kernel.org>
Register 0x1910 unmasks interrupts and legacy INTx interrupts are unmasked
because driver does not support individual masking yet.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/controller/pci-mvebu.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 1ae7718a2e3e..d096289035bc 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -54,9 +54,10 @@
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_INT_CAUSE_OFF 0x1900
+#define PCIE_INT_UNMASK_OFF 0x1910
+#define PCIE_INT_INTX(i) BIT(24+i)
#define PCIE_INT_PM_PME BIT(28)
-#define PCIE_MASK_OFF 0x1910
-#define PCIE_MASK_ENABLE_INTS 0x0f000000
+#define PCIE_INT_ALL_MASK GENMASK(31, 0)
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_CTRL_RC_MODE BIT(1)
@@ -235,7 +236,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
{
- u32 ctrl, lnkcap, cmd, dev_rev, mask;
+ u32 ctrl, lnkcap, cmd, dev_rev, unmask;
/* Setup PCIe controller to Root Complex mode. */
ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
@@ -288,10 +289,19 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
/* Point PCIe unit MBUS decode windows to DRAM space. */
mvebu_pcie_setup_wins(port);
- /* Enable interrupt lines A-D. */
- mask = mvebu_readl(port, PCIE_MASK_OFF);
- mask |= PCIE_MASK_ENABLE_INTS;
- mvebu_writel(port, mask, PCIE_MASK_OFF);
+ /*
+ * Unmask all legacy INTx interrupts as driver does not provide a way
+ * for masking and unmasking of individual legacy INTx interrupts.
+ * Legacy INTx are reported via one shared GIC source and therefore
+ * kernel cannot distinguish which individual legacy INTx was triggered.
+ * These interrupts are shared, so it should not cause any issue. Just
+ * performance penalty as every PCIe interrupt handler needs to be
+ * called when some interrupt is triggered.
+ */
+ unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
+ unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) |
+ PCIE_INT_INTX(2) | PCIE_INT_INTX(3);
+ mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
}
static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
@@ -1450,7 +1460,7 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
mvebu_writel(port, cmd, PCIE_CMD_OFF);
/* Mask all interrupt sources. */
- mvebu_writel(port, 0, PCIE_MASK_OFF);
+ mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
/* Free config space for emulated root bridge. */
pci_bridge_emul_cleanup(&port->bridge);
--
2.20.1
next prev parent reply other threads:[~2022-02-22 15:51 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 15:50 [PATCH v4 00/12] PCI: mvebu: subsystem ids, AER and INTx Pali Rohár
2022-02-22 15:50 ` [PATCH v4 01/12] PCI: pci-bridge-emul: Re-arrange register tests Pali Rohár
2022-02-22 15:50 ` [PATCH v4 02/12] PCI: pci-bridge-emul: Add support for PCIe extended capabilities Pali Rohár
2022-02-22 15:50 ` [PATCH v4 03/12] PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability Pali Rohár
2022-02-22 15:50 ` [PATCH v4 04/12] dt-bindings: PCI: mvebu: Add num-lanes property Pali Rohár
2022-02-25 0:02 ` Bjorn Helgaas
2022-02-25 12:58 ` Pali Rohár
2022-02-25 17:12 ` Bjorn Helgaas
2022-02-22 15:50 ` [PATCH v4 05/12] PCI: mvebu: Correctly configure x1/x4 mode Pali Rohár
2022-02-25 0:08 ` Bjorn Helgaas
2022-02-25 13:04 ` Pali Rohár
2022-02-22 15:50 ` [PATCH v4 06/12] PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge Pali Rohár
2022-02-22 15:50 ` [PATCH v4 07/12] PCI: mvebu: Add support for Advanced Error Reporting registers " Pali Rohár
2022-02-22 15:50 ` [PATCH v4 08/12] PCI: mvebu: Use child_ops API Pali Rohár
2022-02-22 15:50 ` [PATCH v4 09/12] dt-bindings: PCI: mvebu: Update information about intx interrupts Pali Rohár
2022-02-22 15:50 ` Pali Rohár [this message]
2022-02-22 15:50 ` [PATCH v4 11/12] PCI: mvebu: Implement support for legacy INTx interrupts Pali Rohár
2022-02-25 0:26 ` Bjorn Helgaas
2022-02-22 15:50 ` [PATCH v4 12/12] ARM: dts: armada-385.dtsi: Add definitions for PCIe " Pali Rohár
2022-02-22 16:06 ` (subset) [PATCH v4 00/12] PCI: mvebu: subsystem ids, AER and INTx Lorenzo Pieralisi
2022-02-22 16:11 ` Pali Rohár
2022-02-22 16:15 ` Lorenzo Pieralisi
2022-02-22 16:18 ` Pali Rohár
2022-02-28 16:11 ` Gregory CLEMENT
2022-02-28 17:03 ` Rob Herring
2022-03-01 13:47 ` Gregory CLEMENT
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