From: Mario Limonciello <mario.limonciello@amd.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Andreas Noever <andreas.noever@gmail.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
"open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>,
"open list:RADEON and AMDGPU DRM DRIVERS"
<amd-gfx@lists.freedesktop.org>,
"open list:DRM DRIVERS" <dri-devel@lists.freedesktop.org>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<nouveau@lists.freedesktop.org>,
"open list:X86 PLATFORM DRIVERS"
<platform-driver-x86@vger.kernel.org>
Cc: Michael Jamet <michael.jamet@intel.com>,
Yehezkel Bernat <YehezkelShB@gmail.com>,
Lukas Wunner <lukas@wunner.de>, <Alexander.Deucher@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>
Subject: [PATCH v5 2/7] PCI: Move check for old Apple Thunderbolt controllers into a quirk
Date: Thu, 24 Feb 2022 15:51:11 -0600 [thread overview]
Message-ID: <20220224215116.7138-3-mario.limonciello@amd.com> (raw)
In-Reply-To: <20220224215116.7138-1-mario.limonciello@amd.com>
`pci_bridge_d3_possible` currently checks explicitly for a Thunderbolt
controller to indicate that D3 is possible.
This is used solely for older Apple systems, due to a variety of factors:
* Apple used SW connection manager from the beginning, other manufacturers
used a FW connection manager (ICM)
* Apple supported D3 initially, other manfuacturers didn't introduced this
until the `HotplugSupportInD3` _DSD was introduced in ~2015.
Apple has stopped creating new machines with Intel Thunderbolt controllers,
and all other manufacturers now support D3 via `HotPlugSupportInD3` so
this should be a fixed list.
Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/pci/pci.c | 17 +++++++----
drivers/pci/quirks.c | 67 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 9ecce435fb3f..01557c950c9f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1064,7 +1064,18 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
if (pci_use_mid_pm())
return false;
- return acpi_pci_bridge_d3(dev);
+ if (acpi_pci_bridge_d3(dev))
+ return true;
+
+ /*
+ * This is for Apple machines via a quirk
+ * Non-Apple machines will use the ACPI property with the same name
+ * from `acpi_pci_bridge_d3` to indciate support.
+ */
+ if (device_property_read_bool(&dev->dev, "HotPlugSupportInD3"))
+ return true;
+
+ return false;
}
/**
@@ -2954,10 +2965,6 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
if (pci_bridge_d3_force)
return true;
- /* Even the oldest 2010 Thunderbolt controller supports D3. */
- if (bridge->is_thunderbolt)
- return true;
-
/* Platform might know better if the bridge supports D3 */
if (platform_pci_bridge_d3(bridge))
return true;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index ceeca7d8dd90..f74f50ea0695 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3756,6 +3756,73 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
quirk_apple_poweroff_thunderbolt);
#endif
+/*
+ * The first machines supporting Intel Thunderbolt were released by Apple, and
+ * supported a software based connection manager including D3 support, as far
+ * back as 2010. These machines don't have ACPI companions to declare D3
+ * support.
+ *
+ * Other manufacturers introduced Thunderbolt shortly after but notably did not
+ * support:
+ * - Software based connection manager
+ * - Runtime power management
+ * Power management was handled via the BIOS when nothing was plugged in.
+ * Runtime D3 was later introduced in ~2015 and Microsoft declared when the
+ * `HotPlugSupportInD3` _DSD was present that they would support D3.
+ *
+ * This list is expected to be complete and not grow in the future as Apple
+ * has stopped producing new x86 models with Intel Thunderbolt controllers.
+ */
+static void quirk_apple_d3_thunderbolt(struct pci_dev *dev)
+{
+ struct property_entry properties[] = {
+ PROPERTY_ENTRY_BOOL("HotPlugSupportInD3"),
+ {},
+ };
+
+ if (!x86_apple_machine)
+ return;
+
+ if (device_create_managed_software_node(&dev->dev, properties, NULL))
+ pci_warn(dev, "could not add HotPlugSupportInD3 property");
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_NHI,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_NHI,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI,
+ quirk_apple_d3_thunderbolt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE,
+ quirk_apple_d3_thunderbolt);
+
/*
* Following are device-specific reset methods which can be used to
* reset a single function if other methods (e.g. FLR, PM D0->D3) are
--
2.34.1
next prev parent reply other threads:[~2022-02-24 21:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-24 21:51 [PATCH v5 0/7] Overhaul `is_thunderbolt` Mario Limonciello
2022-02-24 21:51 ` [PATCH v5 1/7] PCI: Move `is_thunderbolt` check for lack of command completed to a quirk Mario Limonciello
2022-02-24 21:51 ` Mario Limonciello [this message]
2022-02-24 21:51 ` [PATCH v5 3/7] PCI: Drop the `is_thunderbolt` attribute from PCI core Mario Limonciello
2022-02-25 1:23 ` Bjorn Helgaas
2022-02-25 1:27 ` Bjorn Helgaas
2022-02-25 16:13 ` Alex Deucher
2022-02-25 17:42 ` Bjorn Helgaas
2022-02-28 10:16 ` Mika Westerberg
2022-02-28 15:33 ` Limonciello, Mario
2022-02-28 22:13 ` Bjorn Helgaas
2022-02-28 22:32 ` Lukas Wunner
2022-02-28 22:36 ` Limonciello, Mario
2022-03-01 7:04 ` Mika Westerberg
2022-02-24 21:51 ` [PATCH v5 4/7] drm/amd: drop the use of `pci_is_thunderbolt_attached` Mario Limonciello
2022-02-24 21:51 ` [PATCH v5 5/7] drm/nouveau: " Mario Limonciello
2022-02-24 21:51 ` [PATCH v5 6/7] drm/radeon: " Mario Limonciello
2022-02-24 21:51 ` [PATCH v5 7/7] PCI: drop `pci_is_thunderbolt_attached` Mario Limonciello
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