From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
To: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com,
lorenzo.pieralisi@arm.com, agross@kernel.org,
bjorn.andersson@linaro.org, svarbanov@mm-sol.com,
bhelgaas@google.com, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com,
linux-clk@vger.kernel.org, Vinod Koul <vkoul@kernel.org>
Subject: [PATCH v2 4/7] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs
Date: Tue, 1 Mar 2022 12:55:08 +0530 [thread overview]
Message-ID: <20220301072511.117818-5-bhupesh.sharma@linaro.org> (raw)
In-Reply-To: <20220301072511.117818-1-bhupesh.sharma@linaro.org>
SM8150 has multiple (different) PHY versions:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
Add support for these with relevant init sequence.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 8ea87c69f463..0805c1bab690 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] = {
"aux", "cfg_ahb", "ref", "refgen",
};
+/* the pcie phy on sm8150 doesn't have a ref clock */
+static const char * const sm8150_pciephy_clk_l[] = {
+ "aux", "cfg_ahb", "refgen",
+};
+
static const char * const qmp_v4_phy_clk_l[] = {
"aux", "ref_clk_src", "ref", "com_aux",
};
@@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.pwrdn_delay_max = 1005, /* us */
};
+static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 1,
+
+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
+ .clk_list = sm8150_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .start_ctrl = PCS_START | SERDES_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
+static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 2,
+
+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
+ .clk_list = sm8150_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .start_ctrl = PCS_START | SERDES_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+ .is_dual_lane_phy = true,
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.type = PHY_TYPE_PCIE,
.nlanes = 1,
@@ -6004,6 +6088,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sm6115-qmp-ufs-phy",
.data = &sm6115_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
+ .data = &sm8150_qmp_gen3x1_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
+ .data = &sm8150_qmp_gen3x2_pciephy_cfg,
}, {
.compatible = "qcom,sm8150-qmp-ufs-phy",
.data = &sm8150_ufsphy_cfg,
--
2.35.1
next prev parent reply other threads:[~2022-03-01 7:26 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 1/7] dt-bindings: pci: qcom: Document PCIe bindings " Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 2/7] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 3/7] clk: qcom: gcc: Add PCIE_0_GDSC and PCIE_1_GDSC for SM8150 Bhupesh Sharma
2022-03-01 7:25 ` Bhupesh Sharma [this message]
2022-03-01 7:25 ` [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support Bhupesh Sharma
2022-03-01 11:43 ` Dmitry Baryshkov
2022-03-02 12:19 ` Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150 Bhupesh Sharma
2022-03-01 11:59 ` Dmitry Baryshkov
2022-03-02 12:15 ` Bhupesh Sharma
2022-03-02 0:07 ` Bjorn Helgaas
2022-03-02 12:17 ` Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 7/7] arm64: dts: qcom: sa8155: Enable pcie nodes Bhupesh Sharma
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