From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF14FC433FE for ; Thu, 10 Mar 2022 07:55:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240071AbiCJH4s (ORCPT ); Thu, 10 Mar 2022 02:56:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232086AbiCJH4r (ORCPT ); Thu, 10 Mar 2022 02:56:47 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 376BE132972 for ; Wed, 9 Mar 2022 23:55:47 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id o26so4063101pgb.8 for ; Wed, 09 Mar 2022 23:55:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=OQBsjCcejQbyJJGyzapc2EGUZYnB0tQO4FtR1E/5QlY=; b=GhQ4NDFBdbHmPzn70Bbfq/QEou1xcdng/QxmvueRqE+ox1zfZRwlsNcWZomP1sfJ9U NWMWYoLmGWHiSPvhCUSrq37wrrj3fXrXYpz1odZrGMpEvGHQDBWPWnH8GJKRIqJxqbzm LkpSwuwaRvzQyLB08TThzFcP7WojEAgMLzFauCbmA9sSM2esuaJ/UokAXQpin0hzrZx/ LPPKLrySfBObDXrDVzjmi1ggAO30dOUKzrmAL/QrMxn/DmDofvNctwTB+QOJfzxe8ffj JCg6cZImb9IGyyAQfzezdSF3uBJy22fE7383I5h2gwJ+6t5n0P2DlbJkc9DMHafmgt2b 2bFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=OQBsjCcejQbyJJGyzapc2EGUZYnB0tQO4FtR1E/5QlY=; b=3Fe/ohEFk2SxNoP34uvwcXQhdFred86vK0MInL1hALeGdyUFdMTSPGGS2UZLhp72Bw 4UhJkYqoG963zyJC01pqNsFAlY6HLPjDfnuWzZXEb46Sj9wVx1SA8gtyNqoG0NkmH0aw 6nF4uhDIVjUg6tMpVukYZ1VjrS0WkMOXKixRTa6ku/X7BZBxpNSMir2W6QM4f09tnrEd 7o9rzNfPYdH0jMVoqtz4GDDMBlsaU1M2rmi6winCyFmrzUsNWLKhdWocYaUEzepvx7PV z/DvXGPr8sIdhZv5QkvDVzLgB97wA4jitMZiFsi66tOk+UBZbttYdXg41Adqoqm7Ea5J C9AA== X-Gm-Message-State: AOAM531vnGCoYljNQZSoGW6AsUad3rtevMD8gDYuCD0H+Hvin/OTh3C7 L/rTjXLATVZTpgVyFxxuoB0G X-Google-Smtp-Source: ABdhPJyi2jrr7yFXTP9/Gv1viZ6ABjSTsWguBqXmbav4mBYvPbfBOFr2FipuQHbHhZiMUfIeNSLRGg== X-Received: by 2002:a05:6a00:16ce:b0:4ce:118f:8e4f with SMTP id l14-20020a056a0016ce00b004ce118f8e4fmr3800334pfc.56.1646898946452; Wed, 09 Mar 2022 23:55:46 -0800 (PST) Received: from thinkpad ([117.193.208.22]) by smtp.gmail.com with ESMTPSA id t1-20020a634441000000b00372cb183243sm4812028pgk.1.2022.03.09.23.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Mar 2022 23:55:46 -0800 (PST) Date: Thu, 10 Mar 2022 13:25:39 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: gustavo.pimentel@synopsys.com, hongxing.zhu@nxp.com, l.stach@pengutronix.de, linux-imx@nxp.com, linux-pci@vger.kernel.org, dmaengine@vger.kernel.org, lznuaa@gmail.com, vkoul@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org, kw@linux.com, bhelgaas@google.com, shawnguo@kernel.org Subject: Re: [PATCH v3 5/6] dmaengine: dw-edma: add flags at struct dw_edma_chip Message-ID: <20220310075539.GD4869@thinkpad> References: <20220307224750.18055-1-Frank.Li@nxp.com> <20220307224750.18055-5-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220307224750.18055-5-Frank.Li@nxp.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Subject could be: dmaengine: dw-edma: Add support for chip specific flags On Mon, Mar 07, 2022 at 04:47:49PM -0600, Frank Li wrote: > Allow PCI EP probe DMA locally and prevent use of remote MSI > to remote PCI host. > > Add option to force 32bit DBI register access even on > 64-bit systems. i.MX8 hardware only allowed 32bit register > access. > Add a "flags" field to the "struct dw_edma_chip" so that the controller drivers can pass flags that are relevant to the platform. Currently 2 flags are defined: 1. DW_EDMA_CHIP_LOCAL - Used by the controller drivers accessing eDMA locally. Local eDMA access doesn't require generating MSIs to the remote. 2. DW_EDMA_CHIP_32BIT_DBI - Used by the controller drivers like i.MX8 that allows only 32bit access to the DBI region. Thanks, Mani > Signed-off-by: Frank Li > --- > > Resend added dmaengine@vger.kernel.org > > Change from v2 to v3 > - rework commit message > - Change to DW_EDMA_CHIP_32BIT_DBI > - using DW_EDMA_CHIP_LOCAL control msi > - Apply Bjorn's comments, > if (!j) { > control |= DW_EDMA_V0_LIE; > if (!(chan->chip->flags & DW_EDMA_CHIP_LOCAL)) > control |= DW_EDMA_V0_RIE; > } > > if ((chan->chip->flags & DW_EDMA_CHIP_REG32BIT) || > !IS_ENABLED(CONFIG_64BIT)) { > SET_CH_32(...); > SET_CH_32(...); > } else { > SET_CH_64(...); > } > > > Change from v1 to v2 > - none > > drivers/dma/dw-edma/dw-edma-v0-core.c | 20 ++++++++++++-------- > include/linux/dma/edma.h | 9 +++++++++ > 2 files changed, 21 insertions(+), 8 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c > index 6e2f83e31a03a..081cd7997348d 100644 > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c > @@ -307,6 +307,7 @@ u32 dw_edma_v0_core_status_abort_int(struct dw_edma_chip *chip, enum dw_edma_dir > static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) > { > struct dw_edma_burst *child; > + struct dw_edma_chan *chan = chunk->chan; > struct dw_edma_v0_lli __iomem *lli; > struct dw_edma_v0_llp __iomem *llp; > u32 control = 0, i = 0; > @@ -320,9 +321,11 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) > j = chunk->bursts_alloc; > list_for_each_entry(child, &chunk->burst->list, list) { > j--; > - if (!j) > - control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE); > - > + if (!j) { > + control |= DW_EDMA_V0_LIE; > + if (!(chan->chip->flags & DW_EDMA_CHIP_LOCAL)) > + control |= DW_EDMA_V0_RIE; > + } > /* Channel control */ > SET_LL_32(&lli[i].control, control); > /* Transfer size */ > @@ -420,15 +423,16 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > SET_CH_32(chip, chan->dir, chan->id, ch_control1, > (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); > /* Linked list */ > - #ifdef CONFIG_64BIT > - SET_CH_64(chip, chan->dir, chan->id, llp.reg, > - chunk->ll_region.paddr); > - #else /* CONFIG_64BIT */ > + if ((chan->chip->flags & DW_EDMA_CHIP_32BIT_DBI) || > + !IS_ENABLED(CONFIG_64BIT)) { > SET_CH_32(chip, chan->dir, chan->id, llp.lsb, > lower_32_bits(chunk->ll_region.paddr)); > SET_CH_32(chip, chan->dir, chan->id, llp.msb, > upper_32_bits(chunk->ll_region.paddr)); > - #endif /* CONFIG_64BIT */ > + } else { > + SET_CH_64(chip, chan->dir, chan->id, llp.reg, > + chunk->ll_region.paddr); > + } > } > /* Doorbell */ > SET_RW_32(chip, chan->dir, doorbell, > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > index fcfbc0f47f83d..4321f6378ef66 100644 > --- a/include/linux/dma/edma.h > +++ b/include/linux/dma/edma.h > @@ -33,6 +33,12 @@ enum dw_edma_map_format { > EDMA_MF_HDMA_COMPAT = 0x5 > }; > > +/* Probe EDMA engine locally and prevent generate MSI to host side*/ > +#define DW_EDMA_CHIP_LOCAL BIT(0) > + > +/* Only support 32bit DBI register access */ > +#define DW_EDMA_CHIP_32BIT_DBI BIT(1) > + > /** > * struct dw_edma_chip - representation of DesignWare eDMA controller hardware > * @dev: struct device of the eDMA controller > @@ -40,6 +46,8 @@ enum dw_edma_map_format { > * @nr_irqs: total dma irq number > * reg64bit if support 64bit write to register > * @ops DMA channel to IRQ number mapping > + * @flags - DW_EDMA_CHIP_LOCAL > + * - DW_EDMA_CHIP_32BIT_DBI > * @wr_ch_cnt DMA write channel number > * @rd_ch_cnt DMA read channel number > * @rg_region DMA register region > @@ -53,6 +61,7 @@ struct dw_edma_chip { > int id; > int nr_irqs; > const struct dw_edma_core_ops *ops; > + u32 flags; > > void __iomem *reg_base; > > -- > 2.24.0.rc1 >