From: Frank Li <Frank.Li@nxp.com>
To: gustavo.pimentel@synopsys.com, hongxing.zhu@nxp.com,
l.stach@pengutronix.de, linux-imx@nxp.com,
linux-pci@vger.kernel.org, dmaengine@vger.kernel.org,
fancer.lancer@gmail.com, lznuaa@gmail.com
Cc: vkoul@kernel.org, lorenzo.pieralisi@arm.com, robh@kernel.org,
kw@linux.com, bhelgaas@google.com, shawnguo@kernel.org,
manivannan.sadhasivam@linaro.org
Subject: [PATCH v5 7/9] dmaengine: dw-edma: Add support for chip specific flags
Date: Thu, 10 Mar 2022 13:24:55 -0600 [thread overview]
Message-ID: <20220310192457.3090-8-Frank.Li@nxp.com> (raw)
In-Reply-To: <20220310192457.3090-1-Frank.Li@nxp.com>
Add a "flags" field to the "struct dw_edma_chip" so that the controller
drivers can pass flags that are relevant to the platform.
DW_EDMA_CHIP_LOCAL - Used by the controller drivers accessing eDMA
locally. Local eDMA access doesn't require generating MSIs to the remote.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v4 to v5
- split two two patch
- rework commit message
Change from v3 to v4
none
Change from v2 to v3
- rework commit message
- Change to DW_EDMA_CHIP_32BIT_DBI
- using DW_EDMA_CHIP_LOCAL control msi
- Apply Bjorn's comments,
if (!j) {
control |= DW_EDMA_V0_LIE;
if (!(chan->chip->flags & DW_EDMA_CHIP_LOCAL))
control |= DW_EDMA_V0_RIE;
}
if ((chan->chip->flags & DW_EDMA_CHIP_REG32BIT) ||
!IS_ENABLED(CONFIG_64BIT)) {
SET_CH_32(...);
SET_CH_32(...);
} else {
SET_CH_64(...);
}
Change from v1 to v2
- none
drivers/dma/dw-edma/dw-edma-v0-core.c | 9 ++++++---
include/linux/dma/edma.h | 5 +++++
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index 35f2adac93e46..30686bfe1790c 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -301,6 +301,7 @@ u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
{
struct dw_edma_burst *child;
+ struct dw_edma_chan *chan = chunk->chan;
struct dw_edma_v0_lli __iomem *lli;
struct dw_edma_v0_llp __iomem *llp;
u32 control = 0, i = 0;
@@ -314,9 +315,11 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
j = chunk->bursts_alloc;
list_for_each_entry(child, &chunk->burst->list, list) {
j--;
- if (!j)
- control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE);
-
+ if (!j) {
+ control |= DW_EDMA_V0_LIE;
+ if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))
+ control |= DW_EDMA_V0_RIE;
+ }
/* Channel control */
SET_LL_32(&lli[i].control, control);
/* Transfer size */
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
index c2039246fc08c..5816c8bdf9a64 100644
--- a/include/linux/dma/edma.h
+++ b/include/linux/dma/edma.h
@@ -33,12 +33,16 @@ enum dw_edma_map_format {
EDMA_MF_HDMA_COMPAT = 0x5
};
+/* Probe EDMA engine locally and prevent generate MSI to host side*/
+#define DW_EDMA_CHIP_LOCAL BIT(0)
+
/**
* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
* @dev: struct device of the eDMA controller
* @id: instance ID
* @nr_irqs: total dma irq number
* @ops DMA channel to IRQ number mapping
+ * @flags - DW_EDMA_CHIP_LOCAL
* @reg_base DMA register base address
* @ll_wr_cnt DMA write link list number
* @ll_rd_cnt DMA read link list number
@@ -53,6 +57,7 @@ struct dw_edma_chip {
int id;
int nr_irqs;
const struct dw_edma_core_ops *ops;
+ u32 flags;
void __iomem *reg_base;
--
2.24.0.rc1
next prev parent reply other threads:[~2022-03-10 19:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 19:24 [PATCH v5 0/9] Enable designware PCI EP EDMA locally Frank Li
2022-03-10 19:24 ` [PATCH v5 1/9] dmaengine: dw-edma: Detach the private data and chip info structures Frank Li
2022-03-10 19:24 ` [PATCH v5 2/9] dmaengine: dw-edma: remove unused field irq in struct dw_edma_chip Frank Li
2022-03-10 19:24 ` [PATCH v5 3/9] dmaengine: dw-edma: change rg_region to reg_base " Frank Li
2022-03-10 19:24 ` [PATCH v5 4/9] dmaengine: dw-edma: rename wr(rd)_ch_cnt to ll_wr(rd)_cnt " Frank Li
2022-03-10 19:24 ` [PATCH v5 5/9] dmaengine: dw-edma: Fix programming the source & dest addresses for ep Frank Li
2022-03-10 19:24 ` [PATCH v5 6/9] dmaengine: dw-edma: Don't rely on the deprecated "direction" member Frank Li
2022-03-10 19:24 ` Frank Li [this message]
2022-03-10 19:24 ` [PATCH v5 8/9] dmaengine: dw-edma: Add DW_EDMA_CHIP_32BIT_DBI for chip specific flags Frank Li
2022-03-10 19:24 ` [PATCH v5 9/9] PCI: endpoint: functions/pci-epf-test: Support PCI controller DMA Frank Li
2022-03-10 19:45 ` [PATCH v5 0/9] Enable designware PCI EP EDMA locally Serge Semin
2022-03-10 19:58 ` Zhi Li
2022-03-10 20:00 ` Serge Semin
2022-03-11 22:58 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220310192457.3090-8-Frank.Li@nxp.com \
--to=frank.li@nxp.com \
--cc=bhelgaas@google.com \
--cc=dmaengine@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=hongxing.zhu@nxp.com \
--cc=kw@linux.com \
--cc=l.stach@pengutronix.de \
--cc=linux-imx@nxp.com \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=lznuaa@gmail.com \
--cc=manivannan.sadhasivam@linaro.org \
--cc=robh@kernel.org \
--cc=shawnguo@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).