From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Manivannan Sadhasivam <mani@kernel.org>
Subject: [PATCH 4/4] arm64: dts: qcom: sm8250: provide additional MSI interrupts
Date: Mon, 11 Apr 2022 14:49:26 +0300 [thread overview]
Message-ID: <20220411114926.1975363-5-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220411114926.1975363-1-dmitry.baryshkov@linaro.org>
On SM8250 each group of MSI interrupts is mapped to the separate host
interrupt. Describe each of interrupts in the device tree for PCIe0
host.
Tested on Qualcomm RB5 platform with first group of MSI interrupts being
used by the PME and attached ath11k WiFi chip using second group of MSI
interrupts.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a7a7375893cc..ad22a921db7e 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1808,8 +1808,15 @@ pcie0: pci@1c00000 {
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
--
2.35.1
prev parent reply other threads:[~2022-04-11 11:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-11 11:49 [PATCH 0/4] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-04-11 11:49 ` [PATCH 1/4] PCI: qcom: Handle MSI IRQs properly Dmitry Baryshkov
2022-04-13 19:57 ` Bjorn Helgaas
2022-04-11 11:49 ` [PATCH 2/4] dt-bindings: pci: qcom: Document additional PCI MSI interrupts Dmitry Baryshkov
2022-04-12 15:54 ` Rob Herring
2022-04-11 11:49 ` [PATCH 3/4] arm64: dts: qcom: sm8250: remove snps,dw-pcie compatibles Dmitry Baryshkov
2022-04-11 11:49 ` Dmitry Baryshkov [this message]
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