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Sat, 23 Apr 2022 05:49:39 -0700 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V2 6/8] PCI: Disable MSI for Tegra234 root ports Date: Sat, 23 Apr 2022 18:18:56 +0530 Message-ID: <20220423124858.25946-7-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220423124858.25946-1-vidyas@nvidia.com> References: <20220423124858.25946-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a3e4a059-78cc-4b55-1a1a-08da2527c9a4 X-MS-TrafficTypeDiagnostic: CY4PR12MB1720:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qGS3st6AzyYM9UN6lJ2rqrwRwLFs/aXN7zp4+gPhTWoBI8TMNLgKgYU85R6ek3VKORuYvjcX5b3sNLsQYZ+7JxzuHUAjOKw0ZLZpBy0vMzqFU83pl8u7/ilMgBoxkuh15JSXtfz/8TEn8UC7a8kqE5VZGoUe44SxrsNfzVSlDmmaQ80sIt8zQ/jdUq5lACuimNzBZr2ohf9hl13kw0/vyz40aqCZlBq7fMpPUANzQsyoQw1HYeHG6LEAazI5oQf+De4DfcdxqSKHD633jKVW2HkWG20zInC5pzJYrb4qmJJciKhvt1K00Iq0iIYXe7sJ/8ndtcGris7BdNHQEKr0qNOcWmXQ6tKb/W81Wyre2VaPryCNpbLSvezbSP6iDafE6gAYW+CiLSzS417bNJKpj23WTwsnGKm8F+vqgE3OCAjz5ftH8nA+ClG5Iq/kIYinHBRxMhKy2LYmutmRg2kzRvcVihn7iF7A9YPpGqCdpRgIf1+XlT5uom8NvWnLFQYo6amTKUSKZtx64HYpduDjc1lG7c8NaiXsmU5fEVXfG7uqEm7wn0YVPtsKUSSw6UIBNWqGJWrt56LvHomRSQJ7+gEuG2c4c6scRUbCyRXmz2fKdUPrTfQKcidkDREYrUAaiftSvj7mMs76+IZYpwk8/WJQEA+pHZAGbiA9WIAWQXYQ+arO8NGCOB9ktj5RVLxcZA5aYyNq5VcRoMXT3S26WQ== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(8676002)(4326008)(508600001)(7416002)(1076003)(2616005)(8936002)(186003)(336012)(426003)(83380400001)(70586007)(70206006)(5660300002)(47076005)(356005)(2906002)(36860700001)(36756003)(82310400005)(6666004)(7696005)(110136005)(86362001)(81166007)(26005)(40460700003)(6636002)(54906003)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2022 12:50:04.1711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3e4a059-78cc-4b55-1a1a-08da2527c9a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1720 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra234 PCIe rootports don't generate MSI interrupts for PME and AER events. Since PCIe spec (Ref: r4.0 sec 6.1.4.3) doesn't support using a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports service drivers registering their respective ISRs with MSI interrupt and to let only INTx be used for all events. Signed-off-by: Vidya Sagar --- V2: * Addressed review comments from Bjorn i.e. changed the PCIe spec reference to a more relevant section and modified commit message accordingly drivers/pci/quirks.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 41aeaa235132..6ebb4301eb43 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2709,8 +2709,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, nvenet_msi_disable); /* - * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled, - * then the device can't use INTx interrupts. Tegra's PCIe root ports don't + * PCIe spec r4.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled,then the + * device can't use INTx interrupts. Tegra's PCIe root ports don't * generate MSI interrupts for PME and AER events instead only INTx interrupts * are generated. Though Tegra's PCIe root ports can generate MSI interrupts * for other events, since PCIe specification doesn't support using a mix of @@ -2760,6 +2760,15 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, PCI_CLASS_BRIDGE_PCI, 8, pci_quirk_nvidia_tegra_disable_rp_msi); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, + PCI_CLASS_BRIDGE_PCI, 8, + pci_quirk_nvidia_tegra_disable_rp_msi); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, + PCI_CLASS_BRIDGE_PCI, 8, + pci_quirk_nvidia_tegra_disable_rp_msi); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, + PCI_CLASS_BRIDGE_PCI, 8, + pci_quirk_nvidia_tegra_disable_rp_msi); /* * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing -- 2.17.1