From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stephen Boyd" <swboyd@chromium.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Taniya Das" <quic_tdas@quicinc.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: Prasad Malisetty <quic_pmaliset@quicinc.com>,
Johan Hovold <johan+linaro@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH v4 1/5] PCI: qcom: Remove unnecessary pipe_clk handling
Date: Sun, 1 May 2022 22:21:45 +0300 [thread overview]
Message-ID: <20220501192149.4128158-2-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220501192149.4128158-1-dmitry.baryshkov@linaro.org>
QMP PHY driver already does clk_prepare_enable()/_disable() pipe_clk.
Remove extra calls to enable/disable this clock from the PCIe driver, so
that the PHY driver can manage the clock on its own.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 44 ++------------------------
1 file changed, 3 insertions(+), 41 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 57636246cecc..a6becafb6a77 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -128,7 +128,6 @@ struct qcom_pcie_resources_2_3_2 {
struct clk *master_clk;
struct clk *slave_clk;
struct clk *cfg_clk;
- struct clk *pipe_clk;
struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
};
@@ -165,7 +164,6 @@ struct qcom_pcie_resources_2_7_0 {
int num_clks;
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
- struct clk *pipe_clk;
struct clk *pipe_clk_src;
struct clk *phy_pipe_clk;
struct clk *ref_clk_src;
@@ -597,8 +595,7 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
if (IS_ERR(res->slave_clk))
return PTR_ERR(res->slave_clk);
- res->pipe_clk = devm_clk_get(dev, "pipe");
- return PTR_ERR_OR_ZERO(res->pipe_clk);
+ return 0;
}
static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
@@ -613,13 +610,6 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
-static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
-{
- struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
-
- clk_disable_unprepare(res->pipe_clk);
-}
-
static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
@@ -694,22 +684,6 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
return ret;
}
-static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
-{
- struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
- struct dw_pcie *pci = pcie->pci;
- struct device *dev = pci->dev;
- int ret;
-
- ret = clk_prepare_enable(res->pipe_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable pipe clock\n");
- return ret;
- }
-
- return 0;
-}
-
static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
@@ -1198,8 +1172,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
return PTR_ERR(res->ref_clk_src);
}
- res->pipe_clk = devm_clk_get(dev, "pipe");
- return PTR_ERR_OR_ZERO(res->pipe_clk);
+ return 0;
}
static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
@@ -1292,14 +1265,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
if (pcie->cfg->pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
- return clk_prepare_enable(res->pipe_clk);
-}
-
-static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
-{
- struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
-
- clk_disable_unprepare(res->pipe_clk);
+ return 0;
}
static int qcom_pcie_link_up(struct dw_pcie *pci)
@@ -1449,9 +1415,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = {
static const struct qcom_pcie_ops ops_2_3_2 = {
.get_resources = qcom_pcie_get_resources_2_3_2,
.init = qcom_pcie_init_2_3_2,
- .post_init = qcom_pcie_post_init_2_3_2,
.deinit = qcom_pcie_deinit_2_3_2,
- .post_deinit = qcom_pcie_post_deinit_2_3_2,
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
@@ -1478,7 +1442,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = {
.deinit = qcom_pcie_deinit_2_7_0,
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
.post_init = qcom_pcie_post_init_2_7_0,
- .post_deinit = qcom_pcie_post_deinit_2_7_0,
};
/* Qcom IP rev.: 1.9.0 */
@@ -1488,7 +1451,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
.deinit = qcom_pcie_deinit_2_7_0,
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
.post_init = qcom_pcie_post_init_2_7_0,
- .post_deinit = qcom_pcie_post_deinit_2_7_0,
.config_sid = qcom_pcie_config_sid_sm8250,
};
--
2.35.1
next prev parent reply other threads:[~2022-05-01 19:22 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-01 19:21 [PATCH v4 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Dmitry Baryshkov
2022-05-01 19:21 ` Dmitry Baryshkov [this message]
2022-05-02 10:13 ` [PATCH v4 1/5] PCI: qcom: Remove unnecessary pipe_clk handling Manivannan Sadhasivam
2022-05-09 9:41 ` Johan Hovold
2022-05-01 19:21 ` [PATCH v4 2/5] clk: qcom: regmap: add pipe clk implementation Dmitry Baryshkov
2022-05-02 10:10 ` Manivannan Sadhasivam
2022-05-02 10:35 ` Dmitry Baryshkov
2022-05-02 11:10 ` Manivannan Sadhasivam
2022-05-02 11:18 ` Dmitry Baryshkov
2022-05-02 15:06 ` Manivannan Sadhasivam
2022-05-02 15:24 ` Dmitry Baryshkov
2022-05-06 12:54 ` Johan Hovold
2022-05-06 15:25 ` Manivannan Sadhasivam
2022-05-06 12:40 ` Johan Hovold
2022-05-06 13:00 ` Dmitry Baryshkov
2022-05-09 10:29 ` Johan Hovold
2022-05-11 14:17 ` Dmitry Baryshkov
2022-05-13 8:22 ` Johan Hovold
2022-05-11 14:34 ` Manivannan Sadhasivam
2022-05-06 12:31 ` Johan Hovold
2022-05-06 12:40 ` Dmitry Baryshkov
2022-05-09 10:28 ` Johan Hovold
2022-05-09 10:17 ` Johan Hovold
2022-05-01 19:21 ` [PATCH v4 3/5] clk: qcom: gcc-sm8450: use new clk_regmap_pipe_ops for PCIe pipe clocks Dmitry Baryshkov
2022-05-01 19:21 ` [PATCH v4 4/5] clk: qcom: gcc-sc7280: " Dmitry Baryshkov
2022-05-01 19:21 ` [PATCH v4 5/5] PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov
2022-05-09 10:24 ` Johan Hovold
2022-05-11 13:19 ` [PATCH v4 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220501192149.4128158-2-dmitry.baryshkov@linaro.org \
--to=dmitry.baryshkov@linaro.org \
--cc=agross@kernel.org \
--cc=bhelgaas@google.com \
--cc=bjorn.andersson@linaro.org \
--cc=johan+linaro@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mturquette@baylibre.com \
--cc=quic_pmaliset@quicinc.com \
--cc=quic_tdas@quicinc.com \
--cc=swboyd@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).