From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AC58C41535 for ; Thu, 12 May 2022 17:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357054AbiELR3V (ORCPT ); Thu, 12 May 2022 13:29:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347624AbiELR3R (ORCPT ); Thu, 12 May 2022 13:29:17 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DFA526BC86 for ; Thu, 12 May 2022 10:29:16 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id b18so10293257lfv.9 for ; Thu, 12 May 2022 10:29:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=98VvuWwg/UxrQVt2tP9Y2pnp9hUtu4rLQ2/MrJ26H6s=; b=etikO/vHTkOjGYNJ6sZrk78vnq3Fz7c2zQbOnCAfk8rKO8a9LKg7/eTED3ZGiN17rs MhZcYZDZzU4gcoEuGCze82d2IOmtCP+D9MLhVBYfWyFeAkX8dT2S/BaUecScyb/UrhjH vigWaZArSRZpnuUq+Qb6QGHI6DajBVpRfd9wiJRdYmCzK0K2kxuMRYx+7dR9KuTJ4rIQ PQBCg427/FV8uNAMR1c655LkJcKzVmIL6aYn7KQ1mecATgvHInViF8jA4XeJerNv7bsF etLhG7k3YtCAJVCk4tI1xTBcxalEUkfzaj+P+6vW1dvDShoD0r9vHtPZjBjkLCwtp/MG 5TLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=98VvuWwg/UxrQVt2tP9Y2pnp9hUtu4rLQ2/MrJ26H6s=; b=CEBkNvIuf6MQ1HCLo9B8UzdeW0I/larD3Ex98aYAtLcc6cKi8Mg2HVrRamk4wy4gUz 17WyV4Gz0VlUgTsQJjqPEnB7g0Q6HnUps1p/keP6mdkFOm3e3ztx4nUwtvYZzFautgVx m+Sm12yscLKY9vFz225TMlKBCAerHO3yCyDs7t0eQhLLxyyYKfRPS2WkufOOBCIGdhGg ZxZLTKOWcicNGCNdNBddj/tspBuDx+eBvk2zDsW+ECic3uODXoaUK2mhLKrkX5WL5VSu qsXpIgaMrrGwgcjecicDxKT7A5VYG3leLMXFc6GPSi/9rATKWoILNkl25r9XxuBjCCHv oa4Q== X-Gm-Message-State: AOAM530oK0Xbm9I38PEq4EWkOkHCA253ypSsLurWcC0hLehbpxyolA8j uarTZ+hryTOuaOuFFCgXp8ql2g== X-Google-Smtp-Source: ABdhPJwr5pCZazlGCwTGY5QlVE/vL8NCRFlEF9LjDXqvRgpFJUF8qdh9qOZxhEwG708cY5+WRjpxwg== X-Received: by 2002:a05:6512:3091:b0:473:bfb1:8da0 with SMTP id z17-20020a056512309100b00473bfb18da0mr624457lfd.154.1652376554273; Thu, 12 May 2022 10:29:14 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id y10-20020a2e95ca000000b0024f3d1dae9asm11520ljh.34.2022.05.12.10.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 10:29:13 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Michael Turquette , Stephen Boyd , Johan Hovold , Manivannan Sadhasivam Cc: Prasad Malisetty , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-clk@vger.kernel.org, Prasad Malisetty Subject: [PATCH v5 5/5] PCI: qcom: Drop manual pipe_clk_src handling Date: Thu, 12 May 2022 20:29:09 +0300 Message-Id: <20220512172909.2436302-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512172909.2436302-1-dmitry.baryshkov@linaro.org> References: <20220512172909.2436302-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable(). Drop redundant code letting the pipe clock driver park the clock to the safe bi_tcxo parent automatically. Cc: Prasad Malisetty Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 39 +------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a6becafb6a77..b48c899bcc97 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk_src; - struct clk *phy_pipe_clk; - struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -192,7 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; unsigned int has_aggre0_clk:1; @@ -1158,20 +1154,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->cfg->pipe_clk_need_muxing) { - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); - if (IS_ERR(res->pipe_clk_src)) - return PTR_ERR(res->pipe_clk_src); - - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); - if (IS_ERR(res->phy_pipe_clk)) - return PTR_ERR(res->phy_pipe_clk); - - res->ref_clk_src = devm_clk_get(dev, "ref"); - if (IS_ERR(res->ref_clk_src)) - return PTR_ERR(res->ref_clk_src); - } - return 0; } @@ -1189,10 +1171,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1254,18 +1232,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -} -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - - return 0; + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1441,7 +1409,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1450,7 +1417,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -1488,7 +1454,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre0_clk = true, .has_aggre1_clk = true, }; @@ -1496,14 +1461,12 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, - .pipe_clk_need_muxing = true, }; static const struct dw_pcie_ops dw_pcie_ops = { -- 2.35.1