From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Johan Hovold <johan@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v9 05/10] PCI: dwc: split MSI IRQ parsing/allocation to a separate function
Date: Fri, 13 May 2022 16:16:50 +0300 [thread overview]
Message-ID: <20220513131655.2927616-6-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220513131655.2927616-1-dmitry.baryshkov@linaro.org>
Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init()
function. The code is complex enough to warrant a separate function.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../pci/controller/dwc/pcie-designware-host.c | 97 +++++++++++--------
1 file changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 5f6590929319..983fff735d7e 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -288,6 +288,59 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
+static int dw_pcie_msi_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct platform_device *pdev = to_platform_device(pci->dev);
+ int ret;
+ u32 ctrl, num_ctrls;
+
+ num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+ pp->irq_mask[ctrl] = ~0;
+
+ if (!pp->msi_irq[0]) {
+ int irq = platform_get_irq_byname_optional(pdev, "msi");
+
+ if (irq < 0) {
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+ }
+ pp->msi_irq[0] = irq;
+ }
+
+ pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
+
+ ret = dw_pcie_allocate_domains(pp);
+ if (ret)
+ return ret;
+
+ for (ctrl = 0; ctrl < num_ctrls; ctrl++)
+ if (pp->msi_irq[ctrl] > 0)
+ irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
+ dw_chained_msi_isr,
+ pp);
+
+ ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
+ if (ret)
+ dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
+
+ pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
+ sizeof(pp->msi_msg),
+ DMA_FROM_DEVICE,
+ DMA_ATTR_SKIP_CPU_SYNC);
+ ret = dma_mapping_error(pci->dev, pp->msi_data);
+ if (ret) {
+ dev_err(pci->dev, "Failed to map MSI data: %d\n", ret);
+ pp->msi_data = 0;
+ dw_pcie_free_msi(pp);
+ return ret;
+ }
+
+ return 0;
+}
+
int dw_pcie_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -365,49 +418,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (ret < 0)
return ret;
} else if (pp->has_msi_ctrl) {
- u32 ctrl, num_ctrls;
-
- num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
- for (ctrl = 0; ctrl < num_ctrls; ctrl++)
- pp->irq_mask[ctrl] = ~0;
-
- if (!pp->msi_irq[0]) {
- int irq = platform_get_irq_byname_optional(pdev, "msi");
-
- if (irq < 0) {
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
- }
- pp->msi_irq[0] = irq;
- }
-
- pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
-
- ret = dw_pcie_allocate_domains(pp);
- if (ret)
+ ret = dw_pcie_msi_host_init(pp);
+ if (ret < 0)
return ret;
-
- for (ctrl = 0; ctrl < num_ctrls; ctrl++)
- if (pp->msi_irq[ctrl] > 0)
- irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
- dw_chained_msi_isr,
- pp);
-
- ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
- if (ret)
- dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
-
- pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
- sizeof(pp->msi_msg),
- DMA_FROM_DEVICE,
- DMA_ATTR_SKIP_CPU_SYNC);
- ret = dma_mapping_error(pci->dev, pp->msi_data);
- if (ret) {
- dev_err(pci->dev, "Failed to map MSI data: %d\n", ret);
- pp->msi_data = 0;
- goto err_free_msi;
- }
}
}
--
2.35.1
next prev parent reply other threads:[~2022-05-13 13:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-13 13:16 [PATCH v9 00/10] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 01/10] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 02/10] PCI: dwc: Propagate error from dma_mapping_error() Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 03/10] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 04/10] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-05-13 13:16 ` Dmitry Baryshkov [this message]
2022-05-13 13:16 ` [PATCH v9 06/10] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 07/10] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 08/10] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 09/10] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-05-13 13:16 ` [PATCH v9 10/10] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
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