From: Frank Wunderlich <linux@fw-web.de> To: linux-rockchip@lists.infradead.org Cc: "Frank Wunderlich" <frank-w@public-files.de>, "Bjorn Helgaas" <bhelgaas@google.com>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Heiko Stuebner" <heiko@sntech.de>, "Kishon Vijay Abraham I" <kishon@ti.com>, "Vinod Koul" <vkoul@kernel.org>, "Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>, "Krzysztof Wilczyński" <kw@linux.com>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Johan Jonker" <jbx6244@gmail.com>, "Peter Geis" <pgwipeout@gmail.com>, "Michael Riesch" <michael.riesch@wolfvision.net>, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [RFC v3 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes Date: Sat, 14 May 2022 13:59:45 +0200 [thread overview] Message-ID: <20220514115946.8858-5-linux@fw-web.de> (raw) In-Reply-To: <20220514115946.8858-1-linux@fw-web.de> From: Frank Wunderlich <frank-w@public-files.de> Add nodes to rk356x devicetree to support PCIe v3. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix from Peter: change bus-range and msi-map, msi-map needs to start from 0x0 v2: - change to compatible with soc-part - change rockchip,bifurcation to vendor unspecific bifurcation --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5eafddf62edc..6dbe73c9cddf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { reg = <0x0 0xfe190200 0x0 0x20>; }; + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0400000 0x0 0x00400000>, + <0x0 0xfe270000 0x0 0x00010000>, + <0x3 0x40000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x41000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x41100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0800000 0x0 0x00400000>, + <0x0 0xfe280000 0x0 0x00010000>, + <0x3 0x80000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x81000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x81100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; + }; + }; + gmac0: ethernet@fe2a0000 { compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe2a0000 0x0 0x10000>; -- 2.25.1
next prev parent reply other threads:[~2022-05-14 12:00 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-14 11:59 [RFC v3 0/5] RK3568 PCIe V3 support Frank Wunderlich 2022-05-14 11:59 ` [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy Frank Wunderlich 2022-05-14 20:44 ` Krzysztof Kozlowski 2022-05-14 23:14 ` Rob Herring 2022-05-15 11:49 ` Aw: " Frank Wunderlich 2022-05-16 17:35 ` Rob Herring 2022-05-16 19:21 ` Frank Wunderlich 2022-05-18 15:55 ` Rob Herring 2022-05-20 11:50 ` Aw: " Frank Wunderlich 2022-06-02 13:47 ` Frank Wunderlich 2022-05-14 11:59 ` [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf Frank Wunderlich 2022-05-14 20:43 ` Krzysztof Kozlowski 2022-05-14 11:59 ` [RFC v3 3/5] phy: rockchip: Support PCIe v3 Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich [this message] 2022-05-14 11:59 ` [RFC v3 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Frank Wunderlich
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