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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v2-20020a056870310200b000e686d1386csm5670158oaa.6.2022.05.16.10.35.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 10:35:38 -0700 (PDT) Received: (nullmailer pid 2952486 invoked by uid 1000); Mon, 16 May 2022 17:35:37 -0000 Date: Mon, 16 May 2022 12:35:37 -0500 From: Rob Herring To: Frank Wunderlich Cc: Frank Wunderlich , Michael Riesch , Vinod Koul , Johan Jonker , linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Bjorn Helgaas , Philipp Zabel , Lorenzo Pieralisi , Peter Geis , Heiko Stuebner , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= Subject: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy Message-ID: <20220516173537.GA2942634-robh@kernel.org> References: <20220514115946.8858-1-linux@fw-web.de> <20220514115946.8858-2-linux@fw-web.de> <1652570081.002742.3276245.nullmailer@robh.at.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > Hi > > > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > > Von: "Rob Herring" > > > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > > From: Frank Wunderlich > > > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > > > Signed-off-by: Frank Wunderlich > > > > > > --- > > > v3: > > > - drop quotes > > > - drop rk3588 > > > - make clockcount fixed to 3 > > > - full path for binding header file > > > - drop phy-mode and its header and add lane-map > > > > > > v2: > > > dt-bindings: rename yaml for PCIe v3 > > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > > > changes in pcie3 phy yaml > > > - change clock names to ordered const list > > > - extend pcie30-phymode description > > > - add phy-cells to required properties > > > - drop unevaluatedProperties > > > - example with 1 clock each line > > > - use default property instead of text describing it > > > - update license > > > --- > > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > > 1 file changed, 82 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > > False schema does not allow 3 > > 1 was expected > > 3 is greater than the maximum of 2 > > hint: "minItems" is only needed if less than the "items" list length > > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] > > seems this is fixed when i remove the "minItems: 3" from clock names > (which is already fixed length because of the list). Yes. > needed to change type of lane-map to this: > > $ref: /schemas/types.yaml#/definitions/uint8-array Why? That's not a standard property though, so needs a 'rockchip' prefix. Though maybe a common property would be appropriate here. > then it looks clean for it.... > > -m causes many errors unrelated to this schema-file even if i pass > DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml The fix is fixing the remaining 40 or so '-m' errors. Rob