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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id r196-20020acaa8cd000000b00325cda1ffa5sm4175145oie.36.2022.05.16.14.07.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 14:07:05 -0700 (PDT) Received: (nullmailer pid 3288693 invoked by uid 1000); Mon, 16 May 2022 21:07:04 -0000 Date: Mon, 16 May 2022 16:07:04 -0500 From: Rob Herring To: Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 13/17] PCI: dwc: Verify in/out regions against iATU constraints Message-ID: <20220516210704.GI3209795-robh@kernel.org> References: <20220503214638.1895-1-Sergey.Semin@baikalelectronics.ru> <20220503214638.1895-14-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220503214638.1895-14-Sergey.Semin@baikalelectronics.ru> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, May 04, 2022 at 12:46:34AM +0300, Serge Semin wrote: > Since the DWC PCIe driver private data now contains the iATU inbound and > outbound regions constraints info like alignment, minimum and maximum > limits, we can use them to make the in- and outbound iATU regions setup > methods more strict to the ranges a callee tries to specify. That will > give us the safer dw_pcie_prog_outbound_atu(), > dw_pcie_prog_ep_outbound_atu() and dw_pcie_prog_inbound_atu() functions. > > First of all let's update the outbound ATU entries setup methods to > returning the operation status. The methods will fail either in case if > the range is failed to be activated or the passed region doesn't fulfill > iATU constraints. Secondly the passed to the > dw_pcie_prog_{ep_}outbound_atu() methods region-related parameters are > verified against the detected iATU regions constraints. In particular the > region limit address must not overflow the lower/upper limit CSR RW-fields > otherwise the specified range will be just silently clamped. That > verification will also protect the code from having u64 type overflow. > Secondly let's make sure base address (CPU-address), target address > (PCI-address) and size are properly aligned. Unaligned ranges will be > silently aligned down (addresses) and up (limit) on writing the values to > the corresponding registers, which in it turn may lead to unpredictable > results like ranges virtual overlap. Finally the CPU-address alignment > needs to be verified in the dw_pcie_prog_inbound_atu() method too as the > DWC PCIe RC/EP registers manual demands seeing the lower bits of the in- > and outbound iATU base address are always zeros. > > Signed-off-by: Serge Semin > --- > drivers/pci/controller/dwc/pcie-designware.c | 39 +++++++++++++------- > drivers/pci/controller/dwc/pcie-designware.h | 10 ++--- > 2 files changed, 30 insertions(+), 19 deletions(-) Reviewed-by: Rob Herring