[PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Serge Semin]

This patchset is an initial one in the series created in the framework
of my Baikal-T1 PCIe/eDMA-related work:

[1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
[2: In-progress v1] PCI: dwc: Various fixes and cleanups
Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
[3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
Link: https://lore.kernel.org/linux-pci/20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru/
[4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
Link: https://lore.kernel.org/linux-pci/20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru/

Since some of the patches in the later patchsets depend on the
modifications introduced here, @Lorenzo could you please merge this series
through your PCIe subsystem repo? After getting all the required ack'es of
course.

Short summary regarding this patchset. A few more modifications are
introduced here to finally finish the Baikal-T1 CCU unit support up and
prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
all it turned out I specified wrong DW xGMAC PTP reference clock divider
in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
joint xGMAC Ref and PTP clock instead of having them separately defined.
The SoC manual describes these clocks as separate fixed clock wrappers.
Finally in order to close the SoC clock/reset support up we need to add
the DDR and PCIe interfaces reset controls support. It's done in two
steps. First I've moved the reset-controls-related code into a dedicated
module. Then the DDR/PCIe reset-control functionality is added.

Link: https://lore.kernel.org/linux-pci/20220324010905.15589-1-Sergey.Semin@baikalelectronics.ru/
Changelog v2:
- Resubmit the series with adding @Philipp to the list of the recipients.

Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
Changelog v3:
- Rebased from v5.17 onto v5.18-rc3.
- No comments. Just resend the series.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Rob Herring <robh@kernel.org>
Cc: "Krzysztof Wilczyński" <kw@linux.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-clk@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Serge Semin (4):
  clk: baikal-t1: Fix invalid xGMAC PTP clock divider
  clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
  clk: baikal-t1: Move reset-controls code into a dedicated module
  clk: baikal-t1: Add DDR/PCIe directly controlled resets support

 drivers/clk/baikal-t1/Kconfig       |  12 +-
 drivers/clk/baikal-t1/Makefile      |   1 +
 drivers/clk/baikal-t1/ccu-div.c     |   1 +
 drivers/clk/baikal-t1/ccu-div.h     |   6 +
 drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
 drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
 drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
 include/dt-bindings/reset/bt1-ccu.h |   9 +
 8 files changed, 482 insertions(+), 86 deletions(-)
 create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
 create mode 100644 drivers/clk/baikal-t1/ccu-rst.h

-- 
2.35.1

[PATCH v3 1/4] clk: baikal-t1: Fix invalid xGMAC PTP clock divider

[Serge Semin]

Most likely due to copy-paste mistake the divider has been set to 10 while
according to the SoC reference manual it's supposed to be 8 thus having
PTP clock frequency of 156.25 MHz.

Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 drivers/clk/baikal-t1/clk-ccu-div.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index f141fda12b09..ea77eec40ddd 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -207,7 +207,7 @@ static const struct ccu_div_info sys_info[] = {
 	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
 			  "eth_clk", CCU_SYS_XGMAC_BASE, 8),
 	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
-			   "eth_clk", 10),
+			   "eth_clk", 8),
 	CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
 			  "eth_clk", CCU_SYS_USB_BASE, 10),
 	CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
-- 
2.35.1

[PATCH v3 2/4] clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent

[Serge Semin]

Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
PTP clocks are generated by two different wrappers with the same constant
divider thus each producing a 156.25 MHz signal. But for some reason both
of these clock sources are gated by a single switch-flag in the CCU
registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
handled independently we need to define a shared parental gate so the base
clock signal would be switched off only if both of the child-clocks are
disabled.

Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 drivers/clk/baikal-t1/ccu-div.c     | 1 +
 drivers/clk/baikal-t1/ccu-div.h     | 6 ++++++
 drivers/clk/baikal-t1/clk-ccu-div.c | 8 +++++---
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
index 4062092d67f9..bbfa3526ee10 100644
--- a/drivers/clk/baikal-t1/ccu-div.c
+++ b/drivers/clk/baikal-t1/ccu-div.c
@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
 		goto err_free_div;
 	}
 	parent_data.fw_name = div_init->parent_name;
+	parent_data.name = div_init->parent_name;
 	hw_init.parent_data = &parent_data;
 	hw_init.num_parents = 1;
 
diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
index 795665caefbd..81fc26be6e75 100644
--- a/drivers/clk/baikal-t1/ccu-div.h
+++ b/drivers/clk/baikal-t1/ccu-div.h
@@ -13,6 +13,12 @@
 #include <linux/bits.h>
 #include <linux/of.h>
 
+/*
+ * CCU Divider private clock IDs
+ * @CCU_SYS_INT_CLK: Internal CCU system clock
+ */
+#define CCU_SYS_INT_CLK		-1
+
 /*
  * CCU Divider private flags
  * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index ea77eec40ddd..e544129a7543 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = {
 			  "eth_clk", CCU_SYS_GMAC1_BASE, 5),
 	CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
 			   "eth_clk", 10),
-	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
-			  "eth_clk", CCU_SYS_XGMAC_BASE, 8),
+	CCU_DIV_GATE_INFO(CCU_SYS_INT_CLK, "sys_xgmac_clk",
+			  "eth_clk", CCU_SYS_XGMAC_BASE, 1),
+	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+			   "sys_xgmac_clk", 8),
 	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
-			   "eth_clk", 8),
+			   "sys_xgmac_clk", 8),
 	CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
 			  "eth_clk", CCU_SYS_USB_BASE, 10),
 	CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
-- 
2.35.1

[PATCH v3 3/4] clk: baikal-t1: Move reset-controls code into a dedicated module

[Serge Semin]

Before adding the directly controlled resets support it's reasonable to
move the existing resets control functionality into a dedicated object for
the sake of the CCU dividers clock driver simplification. After the new
functionality is added clk-ccu-div.c would have got to a mixture of the
weakly dependent clocks and resets methods. Splitting the methods up into
the two objects will make code easier to read especially seeing it isn't
that hard to do.

As before the CCU reset module will support the trigger-like CCU resets
only, which are responsible for the AXI-bus, APB-bus and SATA-ref blocks
reset. The assert/de-assert-capable reset controls support will be added
in the next commit.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 drivers/clk/baikal-t1/Kconfig       |  12 +-
 drivers/clk/baikal-t1/Makefile      |   1 +
 drivers/clk/baikal-t1/ccu-rst.c     | 258 ++++++++++++++++++++++++++++
 drivers/clk/baikal-t1/ccu-rst.h     |  60 +++++++
 drivers/clk/baikal-t1/clk-ccu-div.c |  94 ++--------
 5 files changed, 342 insertions(+), 83 deletions(-)
 create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
 create mode 100644 drivers/clk/baikal-t1/ccu-rst.h

diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig
index 03102f1094bc..666de354d513 100644
--- a/drivers/clk/baikal-t1/Kconfig
+++ b/drivers/clk/baikal-t1/Kconfig
@@ -29,7 +29,6 @@ config CLK_BT1_CCU_PLL
 
 config CLK_BT1_CCU_DIV
 	bool "Baikal-T1 CCU Dividers support"
-	select RESET_CONTROLLER
 	select MFD_SYSCON
 	default MIPS_BAIKAL_T1
 	help
@@ -39,4 +38,15 @@ config CLK_BT1_CCU_DIV
 	  either gateable or ungateable. Some of the CCU dividers can be as well
 	  used to reset the domains they're supplying clock to.
 
+config CLK_BT1_CCU_RST
+	bool "Baikal-T1 CCU Resets support"
+	select RESET_CONTROLLER
+	select MFD_SYSCON
+	default MIPS_BAIKAL_T1
+	help
+	  Enable this to support the CCU reset blocks responsible for the
+	  AXI-bus and some subsystems reset. These are mainly the trigger-based
+	  reset controls but there are several lines which can be directly
+	  asserted/de-asserted (PCIe and DDR sub-domains).
+
 endif
diff --git a/drivers/clk/baikal-t1/Makefile b/drivers/clk/baikal-t1/Makefile
index b3b9590b95ed..9c3637de9407 100644
--- a/drivers/clk/baikal-t1/Makefile
+++ b/drivers/clk/baikal-t1/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
 obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
+obj-$(CONFIG_CLK_BT1_CCU_RST) += ccu-rst.o
diff --git a/drivers/clk/baikal-t1/ccu-rst.c b/drivers/clk/baikal-t1/ccu-rst.c
new file mode 100644
index 000000000000..5e33c3ce962a
--- /dev/null
+++ b/drivers/clk/baikal-t1/ccu-rst.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
+ *
+ * Authors:
+ *   Serge Semin <Sergey.Semin@baikalelectronics.ru>
+ *
+ * Baikal-T1 CCU Resets interface driver
+ */
+
+#define pr_fmt(fmt) "bt1-ccu-rst: " fmt
+
+#include <linux/bits.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/printk.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/bt1-ccu.h>
+#include <dt-bindings/reset/bt1-ccu.h>
+
+#include "ccu-div.h"
+#include "ccu-rst.h"
+
+#define CCU_RST_MAP(_rst_id, _clk_id)		\
+	{					\
+		.rst_id = _rst_id,		\
+		.clk_id = _clk_id,		\
+	}
+
+struct ccu_rst_map {
+	unsigned int rst_id;
+	unsigned int clk_id;
+};
+
+struct ccu_rst_data {
+	struct device_node *np;
+	struct regmap *sys_regs;
+
+	unsigned int rsts_num;
+	struct ccu_rst *rsts;
+
+	unsigned int rsts_map_num;
+	const struct ccu_rst_map *rsts_map;
+
+	unsigned int divs_num;
+	struct ccu_div **divs;
+
+	struct reset_controller_dev rcdev;
+};
+#define to_ccu_rst_data(_rcdev) container_of(_rcdev, struct ccu_rst_data, rcdev)
+
+/*
+ * Each AXI-bus clock divider is equipped with the corresponding clock-consumer
+ * domain reset (it's trigger-based).
+ */
+static const struct ccu_rst_map axi_rst_map[] = {
+	CCU_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
+	CCU_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
+	CCU_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
+	CCU_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
+	CCU_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
+	CCU_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
+	CCU_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
+	CCU_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
+	CCU_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
+	CCU_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
+	CCU_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK),
+};
+
+/*
+ * SATA reference clock domain and APB-bus domain are connected with the
+ * trigger-based reset control, which can be activated via the corresponding
+ * clock divider register.
+ */
+static const struct ccu_rst_map sys_rst_map[] = {
+	CCU_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
+	CCU_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
+};
+
+static int ccu_rst_reset(struct reset_controller_dev *rcdev,
+			 unsigned long idx)
+{
+	struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+	struct ccu_rst *rst;
+
+	if (idx >= data->rsts_num) {
+		pr_err("Invalid reset ID %lu specified\n", idx);
+		return -EINVAL;
+	}
+
+	rst = &data->rsts[idx];
+	return ccu_div_reset_domain(rst->div);
+}
+
+static const struct reset_control_ops ccu_rst_ops = {
+	.reset = ccu_rst_reset,
+};
+
+static int ccu_rst_of_idx_get(struct reset_controller_dev *rcdev,
+			      const struct of_phandle_args *rstspec)
+{
+	struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+	unsigned int rst_id, idx;
+
+	rst_id = rstspec->args[0];
+	for (idx = 0; idx < data->rsts_num; ++idx) {
+		if (data->rsts[idx].id == rst_id)
+			break;
+	}
+	if (idx == data->rsts_num) {
+		pr_err("Invalid reset ID %u specified\n", rst_id);
+		return -EINVAL;
+	}
+
+	return idx;
+}
+
+static struct ccu_div *ccu_rst_find_div(struct ccu_rst_data *data,
+					unsigned int clk_id)
+{
+	struct ccu_div *div;
+	int idx;
+
+	for (idx = 0; idx < data->divs_num; ++idx) {
+		div = data->divs[idx];
+		if (div->id == clk_id)
+			return div;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static struct ccu_rst_data *ccu_rst_create_data(const struct ccu_rst_init_data *rst_init)
+{
+	struct ccu_rst_data *data;
+	int ret;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return ERR_PTR(-ENOMEM);
+
+	data->np = rst_init->np;
+	data->sys_regs = rst_init->sys_regs;
+	data->divs_num = rst_init->divs_num;
+	data->divs = rst_init->divs;
+	if (of_device_is_compatible(data->np, "baikal,bt1-ccu-axi")) {
+		data->rsts_map_num = ARRAY_SIZE(axi_rst_map);
+		data->rsts_map = axi_rst_map;
+	} else if (of_device_is_compatible(data->np, "baikal,bt1-ccu-sys")) {
+		data->rsts_map_num = ARRAY_SIZE(sys_rst_map);
+		data->rsts_map = sys_rst_map;
+	} else {
+		pr_err("Incompatible DT node '%s' specified\n",
+			of_node_full_name(data->np));
+		ret = -EINVAL;
+		goto err_kfree_data;
+	}
+
+	data->rsts_num = data->rsts_map_num;
+	data->rsts = kcalloc(data->rsts_num, sizeof(*data->rsts), GFP_KERNEL);
+	if (!data->rsts) {
+		ret = -ENOMEM;
+		goto err_kfree_data;
+	}
+
+	return data;
+
+err_kfree_data:
+	kfree(data);
+
+	return ERR_PTR(ret);
+}
+
+static void ccu_rst_free_data(struct ccu_rst_data *data)
+{
+	kfree(data->rsts);
+
+	kfree(data);
+}
+
+static int ccu_rst_init_desc(struct ccu_rst_data *data)
+{
+	struct ccu_rst *rst = data->rsts;
+	unsigned int idx;
+
+	for (idx = 0; idx < data->rsts_map_num; ++idx, ++rst) {
+		const struct ccu_rst_map *map = &data->rsts_map[idx];
+
+		rst->id = map->rst_id;
+		rst->div = ccu_rst_find_div(data, map->clk_id);
+		if (IS_ERR(rst->div)) {
+			pr_err("Couldn't find clock divider '%u'\n", map->clk_id);
+			return PTR_ERR(rst->div);
+		}
+	}
+
+	return 0;
+}
+
+static int ccu_rst_dev_register(struct ccu_rst_data *data)
+{
+	int ret;
+
+	data->rcdev.ops = &ccu_rst_ops;
+	data->rcdev.of_node = data->np;
+	data->rcdev.nr_resets = data->rsts_num;
+	data->rcdev.of_reset_n_cells = 1;
+	data->rcdev.of_xlate = ccu_rst_of_idx_get;
+
+	ret = reset_controller_register(&data->rcdev);
+	if (ret) {
+		pr_err("Couldn't register '%s' reset controller\n",
+			of_node_full_name(data->np));
+	}
+
+	return ret;
+}
+
+static void ccu_rst_dev_unregister(struct ccu_rst_data *data)
+{
+	reset_controller_unregister(&data->rcdev);
+}
+
+struct ccu_rst_data *ccu_rst_hw_register(const struct ccu_rst_init_data *rst_init)
+{
+	struct ccu_rst_data *data;
+	int ret;
+
+	data = ccu_rst_create_data(rst_init);
+	if (IS_ERR(data))
+		return data;
+
+	ret = ccu_rst_init_desc(data);
+	if (ret)
+		goto err_free_data;
+
+	ret = ccu_rst_dev_register(data);
+	if (ret)
+		goto err_free_data;
+
+	return data;
+
+err_free_data:
+	ccu_rst_free_data(data);
+
+	return ERR_PTR(ret);
+}
+
+void ccu_rst_hw_unregister(struct ccu_rst_data *data)
+{
+	ccu_rst_dev_unregister(data);
+
+	ccu_rst_free_data(data);
+}
diff --git a/drivers/clk/baikal-t1/ccu-rst.h b/drivers/clk/baikal-t1/ccu-rst.h
new file mode 100644
index 000000000000..2ef82899dba8
--- /dev/null
+++ b/drivers/clk/baikal-t1/ccu-rst.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
+ *
+ * Baikal-T1 CCU Resets interface driver
+ */
+#ifndef __CLK_BT1_CCU_RST_H__
+#define __CLK_BT1_CCU_RST_H__
+
+#include <linux/regmap.h>
+#include <linux/of.h>
+
+#include "ccu-div.h"
+
+struct ccu_rst_data;
+
+/*
+ * struct ccu_rst_init_data - CCU Resets initialization data
+ * @sys_regs: Baikal-T1 System Controller registers map.
+ * @np: Pointer to the node with the System CCU block.
+ * @divs_num: Number of the CCU dividers the module supports.
+ * @divs: Array of pointers to the CCU divider descriptors.
+ */
+struct ccu_rst_init_data {
+	struct regmap *sys_regs;
+	struct device_node *np;
+
+	unsigned int divs_num;
+	struct ccu_div **divs;
+};
+
+/*
+ * struct ccu_div - CCU Reset descriptor
+ * @id: Reset identifier.
+ * @div: Pointer to the CCU Divider descriptor (can be NULL).
+ */
+struct ccu_rst {
+	unsigned int id;
+	struct ccu_div *div;
+};
+
+#ifdef CONFIG_CLK_BT1_CCU_RST
+
+struct ccu_rst_data *ccu_rst_hw_register(const struct ccu_rst_init_data *init);
+
+void ccu_rst_hw_unregister(struct ccu_rst_data *rcd);
+
+#else
+
+static inline
+struct ccu_rst_data *ccu_rst_hw_register(const struct ccu_rst_init_data *init)
+{
+	return NULL;
+}
+
+static inline void ccu_rst_hw_unregister(struct ccu_rst_data *rcd) {}
+
+#endif
+
+#endif /* __CLK_BT1_CCU_RST_H__ */
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index e544129a7543..1ad7db7ea785 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -24,9 +24,9 @@
 #include <linux/regmap.h>
 
 #include <dt-bindings/clock/bt1-ccu.h>
-#include <dt-bindings/reset/bt1-ccu.h>
 
 #include "ccu-div.h"
+#include "ccu-rst.h"
 
 #define CCU_AXI_MAIN_BASE		0x030
 #define CCU_AXI_DDR_BASE		0x034
@@ -85,12 +85,6 @@
 		.divider = _divider				\
 	}
 
-#define CCU_DIV_RST_MAP(_rst_id, _clk_id)	\
-	{					\
-		.rst_id = _rst_id,		\
-		.clk_id = _clk_id		\
-	}
-
 struct ccu_div_info {
 	unsigned int id;
 	const char *name;
@@ -105,11 +99,6 @@ struct ccu_div_info {
 	unsigned long features;
 };
 
-struct ccu_div_rst_map {
-	unsigned int rst_id;
-	unsigned int clk_id;
-};
-
 struct ccu_div_data {
 	struct device_node *np;
 	struct regmap *sys_regs;
@@ -118,11 +107,8 @@ struct ccu_div_data {
 	const struct ccu_div_info *divs_info;
 	struct ccu_div **divs;
 
-	unsigned int rst_num;
-	const struct ccu_div_rst_map *rst_map;
-	struct reset_controller_dev rcdev;
+	struct ccu_rst_data *rcd;
 };
-#define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
 
 /*
  * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
@@ -169,20 +155,6 @@ static const struct ccu_div_info axi_info[] = {
 			 CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
 };
 
-static const struct ccu_div_rst_map axi_rst_map[] = {
-	CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
-	CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
-};
-
 /*
  * APB-bus clock is marked as critical since it's a main communication bus
  * for the SoC devices registers IO-operations.
@@ -241,11 +213,6 @@ static const struct ccu_div_info sys_info[] = {
 			 CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
 };
 
-static const struct ccu_div_rst_map sys_rst_map[] = {
-	CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
-	CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
-};
-
 static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
 					 unsigned int clk_id)
 {
@@ -261,42 +228,6 @@ static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
 	return ERR_PTR(-EINVAL);
 }
 
-static int ccu_div_reset(struct reset_controller_dev *rcdev,
-			 unsigned long rst_id)
-{
-	struct ccu_div_data *data = to_ccu_div_data(rcdev);
-	const struct ccu_div_rst_map *map;
-	struct ccu_div *div;
-	int idx, ret;
-
-	for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
-		if (map->rst_id == rst_id)
-			break;
-	}
-	if (idx == data->rst_num) {
-		pr_err("Invalid reset ID %lu specified\n", rst_id);
-		return -EINVAL;
-	}
-
-	div = ccu_div_find_desc(data, map->clk_id);
-	if (IS_ERR(div)) {
-		pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
-		return PTR_ERR(div);
-	}
-
-	ret = ccu_div_reset_domain(div);
-	if (ret) {
-		pr_err("Reset isn't supported by divider %s\n",
-			clk_hw_get_name(ccu_div_get_clk_hw(div)));
-	}
-
-	return ret;
-}
-
-static const struct reset_control_ops ccu_div_rst_ops = {
-	.reset = ccu_div_reset,
-};
-
 static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
 {
 	struct ccu_div_data *data;
@@ -310,13 +241,9 @@ static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
 	if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
 		data->divs_num = ARRAY_SIZE(axi_info);
 		data->divs_info = axi_info;
-		data->rst_num = ARRAY_SIZE(axi_rst_map);
-		data->rst_map = axi_rst_map;
 	} else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
 		data->divs_num = ARRAY_SIZE(sys_info);
 		data->divs_info = sys_info;
-		data->rst_num = ARRAY_SIZE(sys_rst_map);
-		data->rst_map = sys_rst_map;
 	} else {
 		pr_err("Incompatible DT node '%s' specified\n",
 			of_node_full_name(np));
@@ -439,18 +366,21 @@ static void ccu_div_clk_unregister(struct ccu_div_data *data)
 
 static int ccu_div_rst_register(struct ccu_div_data *data)
 {
-	int ret;
+	struct ccu_rst_init_data init = {0};
 
-	data->rcdev.ops = &ccu_div_rst_ops;
-	data->rcdev.of_node = data->np;
-	data->rcdev.nr_resets = data->rst_num;
+	init.sys_regs = data->sys_regs;
+	init.np = data->np;
+	init.divs_num = data->divs_num;
+	init.divs = data->divs;
 
-	ret = reset_controller_register(&data->rcdev);
-	if (ret)
+	data->rcd = ccu_rst_hw_register(&init);
+	if (IS_ERR(data->rcd)) {
 		pr_err("Couldn't register divider '%s' reset controller\n",
 			of_node_full_name(data->np));
+		return PTR_ERR(data->rcd);
+	}
 
-	return ret;
+	return 0;
 }
 
 static void ccu_div_init(struct device_node *np)
-- 
2.35.1

Re: [PATCH v3 3/4] clk: baikal-t1: Move reset-controls code into a dedicated module

[Stephen Boyd]

Quoting Serge Semin (2022-05-03 13:57:21)
> Before adding the directly controlled resets support it's reasonable to
> move the existing resets control functionality into a dedicated object for
> the sake of the CCU dividers clock driver simplification. After the new
> functionality is added clk-ccu-div.c would have got to a mixture of the
> weakly dependent clocks and resets methods. Splitting the methods up into
> the two objects will make code easier to read especially seeing it isn't
> that hard to do.
> 
> As before the CCU reset module will support the trigger-like CCU resets
> only, which are responsible for the AXI-bus, APB-bus and SATA-ref blocks
> reset. The assert/de-assert-capable reset controls support will be added
> in the next commit.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> ---
>  drivers/clk/baikal-t1/Kconfig       |  12 +-
>  drivers/clk/baikal-t1/Makefile      |   1 +
>  drivers/clk/baikal-t1/ccu-rst.c     | 258 ++++++++++++++++++++++++++++
>  drivers/clk/baikal-t1/ccu-rst.h     |  60 +++++++
>  drivers/clk/baikal-t1/clk-ccu-div.c |  94 ++--------

Perhaps this should be done via the auxiliary bus by having the clk
driver register the reset driver and have some private API to pass any
data to the reset driver? Then the whole file could be in
drivers/reset/, reviewed and maintained by the reset maintainer.

Re: [PATCH v3 3/4] clk: baikal-t1: Move reset-controls code into a dedicated module

[Serge Semin]

On Tue, May 17, 2022 at 12:37:26AM -0700, Stephen Boyd wrote:
> Quoting Serge Semin (2022-05-03 13:57:21)
> > Before adding the directly controlled resets support it's reasonable to
> > move the existing resets control functionality into a dedicated object for
> > the sake of the CCU dividers clock driver simplification. After the new
> > functionality is added clk-ccu-div.c would have got to a mixture of the
> > weakly dependent clocks and resets methods. Splitting the methods up into
> > the two objects will make code easier to read especially seeing it isn't
> > that hard to do.
> > 
> > As before the CCU reset module will support the trigger-like CCU resets
> > only, which are responsible for the AXI-bus, APB-bus and SATA-ref blocks
> > reset. The assert/de-assert-capable reset controls support will be added
> > in the next commit.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > ---
> >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> >  drivers/clk/baikal-t1/Makefile      |   1 +
> >  drivers/clk/baikal-t1/ccu-rst.c     | 258 ++++++++++++++++++++++++++++
> >  drivers/clk/baikal-t1/ccu-rst.h     |  60 +++++++
> >  drivers/clk/baikal-t1/clk-ccu-div.c |  94 ++--------
> 

> Perhaps this should be done via the auxiliary bus by having the clk
> driver register the reset driver and have some private API to pass any
> data to the reset driver? Then the whole file could be in
> drivers/reset/, reviewed and maintained by the reset maintainer.

I'd rather stick to the current design in the same way as the most of
the OF-based platform clock drivers. Completely splitting the reset
and clock parts isn't that easy is it seems like (though the main part
has been done in the framework of this patchset). AXI/APB-interface
reset controls are tightly coupled with the AXI/APB-clock domains at
least by having the same CSRs. Due to that the corresponding AXI-clock
domains reset functionality will need to be left in the
drivers/clk/baikal-t1/clk-ccu* module. It makes the movement isn't
that justified and will result in needless code complications and the
code coherency worsening.

-Sergey

[PATCH v3 4/4] clk: baikal-t1: Add DDR/PCIe directly controlled resets support

[Serge Semin]

Aside with a set of the trigger-like resets Baikal-T1 CCU provides two
additional blocks with directly controlled reset signals. In particular it
concerns DDR full and initial resets and various PCIe sub-domains resets.
Let's add the direct reset assertion/de-assertion of the corresponding
flags support into the Baikal-T1 CCU driver then. It will be required at
least for the PCIe platform driver. Obviously the DDR controller isn't
supposed to be fully reset in the kernel, so the corresponding controls
are added just for the sake of the interface implementation completeness.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 drivers/clk/baikal-t1/ccu-rst.c     | 117 +++++++++++++++++++++++++++-
 drivers/clk/baikal-t1/ccu-rst.h     |   4 +
 include/dt-bindings/reset/bt1-ccu.h |   9 +++
 3 files changed, 129 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/baikal-t1/ccu-rst.c b/drivers/clk/baikal-t1/ccu-rst.c
index 5e33c3ce962a..186a1491a7d9 100644
--- a/drivers/clk/baikal-t1/ccu-rst.c
+++ b/drivers/clk/baikal-t1/ccu-rst.c
@@ -25,17 +25,33 @@
 #include "ccu-div.h"
 #include "ccu-rst.h"
 
+#define CCU_SYS_DDR_BASE		0x02c
+#define CCU_SYS_PCIE_BASE		0x144
+
 #define CCU_RST_MAP(_rst_id, _clk_id)		\
 	{					\
 		.rst_id = _rst_id,		\
 		.clk_id = _clk_id,		\
 	}
 
+#define CCU_RST_DIR(_rst_id, _base, _ofs)	\
+	{					\
+		.rst_id = _rst_id,		\
+		.base = _base,			\
+		.ofs = _ofs			\
+	}
+
 struct ccu_rst_map {
 	unsigned int rst_id;
 	unsigned int clk_id;
 };
 
+struct ccu_rst_dir {
+	unsigned int rst_id;
+	unsigned int base;
+	unsigned int ofs;
+};
+
 struct ccu_rst_data {
 	struct device_node *np;
 	struct regmap *sys_regs;
@@ -46,6 +62,9 @@ struct ccu_rst_data {
 	unsigned int rsts_map_num;
 	const struct ccu_rst_map *rsts_map;
 
+	unsigned int rsts_dir_num;
+	const struct ccu_rst_dir *rsts_dir;
+
 	unsigned int divs_num;
 	struct ccu_div **divs;
 
@@ -81,6 +100,23 @@ static const struct ccu_rst_map sys_rst_map[] = {
 	CCU_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
 };
 
+/*
+ * DDR and PCIe sub-domains can be reset with directly controlled reset
+ * signals. I wouldn't suggest to reset the DDR controller though at least
+ * while the Linux kernel is working.
+ */
+static const struct ccu_rst_dir sys_rst_dir[] = {
+	CCU_RST_DIR(CCU_SYS_DDR_FULL_RST, CCU_SYS_DDR_BASE, 1),
+	CCU_RST_DIR(CCU_SYS_DDR_INIT_RST, CCU_SYS_DDR_BASE, 2),
+	CCU_RST_DIR(CCU_SYS_PCIE_PCS_PHY_RST, CCU_SYS_PCIE_BASE, 0),
+	CCU_RST_DIR(CCU_SYS_PCIE_PIPE0_RST, CCU_SYS_PCIE_BASE, 4),
+	CCU_RST_DIR(CCU_SYS_PCIE_CORE_RST, CCU_SYS_PCIE_BASE, 8),
+	CCU_RST_DIR(CCU_SYS_PCIE_PWR_RST, CCU_SYS_PCIE_BASE, 9),
+	CCU_RST_DIR(CCU_SYS_PCIE_STICKY_RST, CCU_SYS_PCIE_BASE, 10),
+	CCU_RST_DIR(CCU_SYS_PCIE_NSTICKY_RST, CCU_SYS_PCIE_BASE, 11),
+	CCU_RST_DIR(CCU_SYS_PCIE_HOT_RST, CCU_SYS_PCIE_BASE, 12),
+};
+
 static int ccu_rst_reset(struct reset_controller_dev *rcdev,
 			 unsigned long idx)
 {
@@ -92,12 +128,81 @@ static int ccu_rst_reset(struct reset_controller_dev *rcdev,
 		return -EINVAL;
 	}
 
+	/*
+	 * No CCU divider descriptor means having directly handled reset control,
+	 * which is mapped into the CCU Divider registers.
+	 */
 	rst = &data->rsts[idx];
+	if (!rst->div)
+		return -EOPNOTSUPP;
+
 	return ccu_div_reset_domain(rst->div);
 }
 
+static int ccu_rst_set(struct ccu_rst_data *data,
+		       unsigned long idx, bool high)
+{
+	struct ccu_rst *rst;
+
+	if (idx >= data->rsts_num) {
+		pr_err("Invalid reset ID %lu specified\n", idx);
+		return -EINVAL;
+	}
+
+	/*
+	 * Having CCU divider descriptor means trigger-like reset control so
+	 * direct assertion/de-assertion is unsupported.
+	 */
+	rst = &data->rsts[idx];
+	if (rst->div)
+		return high ? -EOPNOTSUPP : 0;
+
+	return regmap_update_bits(data->sys_regs, rst->reg_ctl,
+				  rst->mask, high ? rst->mask : 0);
+}
+
+static int ccu_rst_assert(struct reset_controller_dev *rcdev,
+			  unsigned long idx)
+{
+	struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+
+	return ccu_rst_set(data, idx, true);
+}
+
+static int ccu_rst_deassert(struct reset_controller_dev *rcdev,
+			    unsigned long idx)
+{
+	struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+
+	return ccu_rst_set(data, idx, false);
+}
+
+static int ccu_rst_status(struct reset_controller_dev *rcdev,
+			  unsigned long idx)
+{
+	struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+	struct ccu_rst *rst;
+	u32 val;
+
+	if (idx >= data->rsts_num) {
+		pr_err("Invalid reset ID %lu specified\n", idx);
+		return -EINVAL;
+	}
+
+	rst = &data->rsts[idx];
+	if (rst->div)
+		return -EOPNOTSUPP;
+
+	regmap_read(data->sys_regs, rst->reg_ctl, &val);
+
+	return !!(val & rst->mask);
+}
+
 static const struct reset_control_ops ccu_rst_ops = {
 	.reset = ccu_rst_reset,
+	.assert = ccu_rst_assert,
+	.deassert = ccu_rst_deassert,
+	.status = ccu_rst_status,
 };
 
 static int ccu_rst_of_idx_get(struct reset_controller_dev *rcdev,
@@ -153,6 +258,8 @@ static struct ccu_rst_data *ccu_rst_create_data(const struct ccu_rst_init_data *
 	} else if (of_device_is_compatible(data->np, "baikal,bt1-ccu-sys")) {
 		data->rsts_map_num = ARRAY_SIZE(sys_rst_map);
 		data->rsts_map = sys_rst_map;
+		data->rsts_dir_num = ARRAY_SIZE(sys_rst_dir);
+		data->rsts_dir = sys_rst_dir;
 	} else {
 		pr_err("Incompatible DT node '%s' specified\n",
 			of_node_full_name(data->np));
@@ -160,7 +267,7 @@ static struct ccu_rst_data *ccu_rst_create_data(const struct ccu_rst_init_data *
 		goto err_kfree_data;
 	}
 
-	data->rsts_num = data->rsts_map_num;
+	data->rsts_num = data->rsts_map_num + data->rsts_dir_num;
 	data->rsts = kcalloc(data->rsts_num, sizeof(*data->rsts), GFP_KERNEL);
 	if (!data->rsts) {
 		ret = -ENOMEM;
@@ -198,6 +305,14 @@ static int ccu_rst_init_desc(struct ccu_rst_data *data)
 		}
 	}
 
+	for (idx = 0; idx < data->rsts_dir_num; ++idx, ++rst) {
+		const struct ccu_rst_dir *dir = &data->rsts_dir[idx];
+
+		rst->id = dir->rst_id;
+		rst->reg_ctl = dir->base;
+		rst->mask = BIT(dir->ofs);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/clk/baikal-t1/ccu-rst.h b/drivers/clk/baikal-t1/ccu-rst.h
index 2ef82899dba8..58347dc8a504 100644
--- a/drivers/clk/baikal-t1/ccu-rst.h
+++ b/drivers/clk/baikal-t1/ccu-rst.h
@@ -33,10 +33,14 @@ struct ccu_rst_init_data {
  * struct ccu_div - CCU Reset descriptor
  * @id: Reset identifier.
  * @div: Pointer to the CCU Divider descriptor (can be NULL).
+ * @reg_ctl: reset control register base address.
+ * @mask: reset flag within the control register.
  */
 struct ccu_rst {
 	unsigned int id;
 	struct ccu_div *div;
+	unsigned int reg_ctl;
+	unsigned int mask;
 };
 
 #ifdef CONFIG_CLK_BT1_CCU_RST
diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h
index 3578e83026bc..c691efaa678f 100644
--- a/include/dt-bindings/reset/bt1-ccu.h
+++ b/include/dt-bindings/reset/bt1-ccu.h
@@ -21,5 +21,14 @@
 
 #define CCU_SYS_SATA_REF_RST		0
 #define CCU_SYS_APB_RST			1
+#define CCU_SYS_DDR_FULL_RST		2
+#define CCU_SYS_DDR_INIT_RST		3
+#define CCU_SYS_PCIE_PCS_PHY_RST	4
+#define CCU_SYS_PCIE_PIPE0_RST		5
+#define CCU_SYS_PCIE_CORE_RST		6
+#define CCU_SYS_PCIE_PWR_RST		7
+#define CCU_SYS_PCIE_STICKY_RST		8
+#define CCU_SYS_PCIE_NSTICKY_RST	9
+#define CCU_SYS_PCIE_HOT_RST		10
 
 #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */
-- 
2.35.1

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Serge Semin]

On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> This patchset is an initial one in the series created in the framework
> of my Baikal-T1 PCIe/eDMA-related work:
> 
> [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> Link: https://lore.kernel.org/linux-pci/20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru/
> [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> Link: https://lore.kernel.org/linux-pci/20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru/
> 
> Since some of the patches in the later patchsets depend on the
> modifications introduced here, @Lorenzo could you please merge this series
> through your PCIe subsystem repo? After getting all the required ack'es of
> course.
> 
> Short summary regarding this patchset. A few more modifications are
> introduced here to finally finish the Baikal-T1 CCU unit support up and
> prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> all it turned out I specified wrong DW xGMAC PTP reference clock divider
> in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> joint xGMAC Ref and PTP clock instead of having them separately defined.
> The SoC manual describes these clocks as separate fixed clock wrappers.
> Finally in order to close the SoC clock/reset support up we need to add
> the DDR and PCIe interfaces reset controls support. It's done in two
> steps. First I've moved the reset-controls-related code into a dedicated
> module. Then the DDR/PCIe reset-control functionality is added.
> 
> Link: https://lore.kernel.org/linux-pci/20220324010905.15589-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v2:
> - Resubmit the series with adding @Philipp to the list of the recipients.
> 
> Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v3:
> - Rebased from v5.17 onto v5.18-rc3.
> - No comments. Just resend the series.

No comments for more than a week. There were no comments in v1 and v2
either. Please at least ack or merge in the series. It would be very
appreciated to merge it in through one repo with the rest of the
patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?

-Sergey

> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Rob Herring <robh@kernel.org>
> Cc: "Krzysztof Wilczyński" <kw@linux.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: linux-clk@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: linux-mips@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> 
> Serge Semin (4):
>   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
>   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
>   clk: baikal-t1: Move reset-controls code into a dedicated module
>   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> 
>  drivers/clk/baikal-t1/Kconfig       |  12 +-
>  drivers/clk/baikal-t1/Makefile      |   1 +
>  drivers/clk/baikal-t1/ccu-div.c     |   1 +
>  drivers/clk/baikal-t1/ccu-div.h     |   6 +
>  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
>  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
>  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
>  include/dt-bindings/reset/bt1-ccu.h |   9 +
>  8 files changed, 482 insertions(+), 86 deletions(-)
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> 
> -- 
> 2.35.1
> 

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Lorenzo Pieralisi]

On Thu, May 12, 2022 at 03:11:56AM +0300, Serge Semin wrote:
> On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> > This patchset is an initial one in the series created in the framework
> > of my Baikal-T1 PCIe/eDMA-related work:
> > 
> > [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> > Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> > [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> > Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> > [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> > Link: https://lore.kernel.org/linux-pci/20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru/
> > [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> > Link: https://lore.kernel.org/linux-pci/20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru/
> > 
> > Since some of the patches in the later patchsets depend on the
> > modifications introduced here, @Lorenzo could you please merge this series
> > through your PCIe subsystem repo? After getting all the required ack'es of
> > course.
> > 
> > Short summary regarding this patchset. A few more modifications are
> > introduced here to finally finish the Baikal-T1 CCU unit support up and
> > prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> > all it turned out I specified wrong DW xGMAC PTP reference clock divider
> > in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> > joint xGMAC Ref and PTP clock instead of having them separately defined.
> > The SoC manual describes these clocks as separate fixed clock wrappers.
> > Finally in order to close the SoC clock/reset support up we need to add
> > the DDR and PCIe interfaces reset controls support. It's done in two
> > steps. First I've moved the reset-controls-related code into a dedicated
> > module. Then the DDR/PCIe reset-control functionality is added.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220324010905.15589-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v2:
> > - Resubmit the series with adding @Philipp to the list of the recipients.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v3:
> > - Rebased from v5.17 onto v5.18-rc3.
> > - No comments. Just resend the series.
> 
> No comments for more than a week. There were no comments in v1 and v2
> either. Please at least ack or merge in the series. It would be very
> appreciated to merge it in through one repo with the rest of the
> patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?

Hi Sergey,

these changes affect the clock tree and have to be reviewed and merged
by the respective maintainers if they think the changes can be accepted.

I don't see any reason why we should, if ACK'ed, take them in the PCI
tree, this series does not apply changes to the PCI tree at all and you
don't need it as a base for future to-be-merged PCI patches either.

So in short, this series has to go through the usual clock tree review
process.

Thanks,
Lorenzo

> -Sergey
> 
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > Cc: Rob Herring <robh@kernel.org>
> > Cc: "Krzysztof Wilczyński" <kw@linux.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-pci@vger.kernel.org
> > Cc: linux-mips@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > 
> > Serge Semin (4):
> >   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
> >   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
> >   clk: baikal-t1: Move reset-controls code into a dedicated module
> >   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> > 
> >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> >  drivers/clk/baikal-t1/Makefile      |   1 +
> >  drivers/clk/baikal-t1/ccu-div.c     |   1 +
> >  drivers/clk/baikal-t1/ccu-div.h     |   6 +
> >  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
> >  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
> >  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
> >  include/dt-bindings/reset/bt1-ccu.h |   9 +
> >  8 files changed, 482 insertions(+), 86 deletions(-)
> >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
> >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> > 
> > -- 
> > 2.35.1
> > 

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Manivannan Sadhasivam]

On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> On Thu, May 12, 2022 at 03:11:56AM +0300, Serge Semin wrote:
> > On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> > > This patchset is an initial one in the series created in the framework
> > > of my Baikal-T1 PCIe/eDMA-related work:
> > > 
> > > [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> > > Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> > > [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> > > Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> > > [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> > > Link: https://lore.kernel.org/linux-pci/20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru/
> > > [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> > > Link: https://lore.kernel.org/linux-pci/20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru/
> > > 
> > > Since some of the patches in the later patchsets depend on the
> > > modifications introduced here, @Lorenzo could you please merge this series
> > > through your PCIe subsystem repo? After getting all the required ack'es of
> > > course.
> > > 
> > > Short summary regarding this patchset. A few more modifications are
> > > introduced here to finally finish the Baikal-T1 CCU unit support up and
> > > prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> > > all it turned out I specified wrong DW xGMAC PTP reference clock divider
> > > in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> > > joint xGMAC Ref and PTP clock instead of having them separately defined.
> > > The SoC manual describes these clocks as separate fixed clock wrappers.
> > > Finally in order to close the SoC clock/reset support up we need to add
> > > the DDR and PCIe interfaces reset controls support. It's done in two
> > > steps. First I've moved the reset-controls-related code into a dedicated
> > > module. Then the DDR/PCIe reset-control functionality is added.
> > > 
> > > Link: https://lore.kernel.org/linux-pci/20220324010905.15589-1-Sergey.Semin@baikalelectronics.ru/
> > > Changelog v2:
> > > - Resubmit the series with adding @Philipp to the list of the recipients.
> > > 
> > > Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> > > Changelog v3:
> > > - Rebased from v5.17 onto v5.18-rc3.
> > > - No comments. Just resend the series.
> > 
> > No comments for more than a week. There were no comments in v1 and v2
> > either. Please at least ack or merge in the series. It would be very
> > appreciated to merge it in through one repo with the rest of the
> > patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?
> 
> Hi Sergey,
> 
> these changes affect the clock tree and have to be reviewed and merged
> by the respective maintainers if they think the changes can be accepted.
> 
> I don't see any reason why we should, if ACK'ed, take them in the PCI
> tree, this series does not apply changes to the PCI tree at all and you
> don't need it as a base for future to-be-merged PCI patches either.
> 
> So in short, this series has to go through the usual clock tree review
> process.
> 

Yes, Stephen should be the one taking these patches through the clk tree. Also,
there is no need to club both pci and clk patches in a single tree. That's
usually done for patches with build dependencies, but here there are none.

Thanks,
Mani

> Thanks,
> Lorenzo
> 
> > -Sergey
> > 
> > > 
> > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Cc: "Krzysztof Wilczyński" <kw@linux.com>
> > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > > Cc: linux-clk@vger.kernel.org
> > > Cc: linux-pci@vger.kernel.org
> > > Cc: linux-mips@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > 
> > > Serge Semin (4):
> > >   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
> > >   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
> > >   clk: baikal-t1: Move reset-controls code into a dedicated module
> > >   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> > > 
> > >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> > >  drivers/clk/baikal-t1/Makefile      |   1 +
> > >  drivers/clk/baikal-t1/ccu-div.c     |   1 +
> > >  drivers/clk/baikal-t1/ccu-div.h     |   6 +
> > >  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
> > >  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
> > >  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
> > >  include/dt-bindings/reset/bt1-ccu.h |   9 +
> > >  8 files changed, 482 insertions(+), 86 deletions(-)
> > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
> > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> > > 
> > > -- 
> > > 2.35.1
> > > 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Serge Semin]

On Thu, May 12, 2022 at 10:41:50PM +0530, Manivannan Sadhasivam wrote:
> On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> > On Thu, May 12, 2022 at 03:11:56AM +0300, Serge Semin wrote:
> > > On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> > > > This patchset is an initial one in the series created in the framework
> > > > of my Baikal-T1 PCIe/eDMA-related work:
> > > > 
> > > > [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> > > > Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> > > > [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> > > > Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> > > > [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> > > > Link: https://lore.kernel.org/linux-pci/20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru/
> > > > [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> > > > Link: https://lore.kernel.org/linux-pci/20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru/
> > > > 
> > > > Since some of the patches in the later patchsets depend on the
> > > > modifications introduced here, @Lorenzo could you please merge this series
> > > > through your PCIe subsystem repo? After getting all the required ack'es of
> > > > course.
> > > > 
> > > > Short summary regarding this patchset. A few more modifications are
> > > > introduced here to finally finish the Baikal-T1 CCU unit support up and
> > > > prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> > > > all it turned out I specified wrong DW xGMAC PTP reference clock divider
> > > > in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> > > > joint xGMAC Ref and PTP clock instead of having them separately defined.
> > > > The SoC manual describes these clocks as separate fixed clock wrappers.
> > > > Finally in order to close the SoC clock/reset support up we need to add
> > > > the DDR and PCIe interfaces reset controls support. It's done in two
> > > > steps. First I've moved the reset-controls-related code into a dedicated
> > > > module. Then the DDR/PCIe reset-control functionality is added.
> > > > 
> > > > Link: https://lore.kernel.org/linux-pci/20220324010905.15589-1-Sergey.Semin@baikalelectronics.ru/
> > > > Changelog v2:
> > > > - Resubmit the series with adding @Philipp to the list of the recipients.
> > > > 
> > > > Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> > > > Changelog v3:
> > > > - Rebased from v5.17 onto v5.18-rc3.
> > > > - No comments. Just resend the series.
> > > 
> > > No comments for more than a week. There were no comments in v1 and v2
> > > either. Please at least ack or merge in the series. It would be very
> > > appreciated to merge it in through one repo with the rest of the
> > > patchsets before the next merge window. @Bjorn, @Lorenzo, @Michael?
> > 

Hello Lorenzo, Manivannan

> > Hi Sergey,
> > 
> > these changes affect the clock tree and have to be reviewed and merged
> > by the respective maintainers if they think the changes can be accepted.
> > 
> > I don't see any reason why we should, if ACK'ed, take them in the PCI
> > tree, this series does not apply changes to the PCI tree at all and you
> > don't need it as a base for future to-be-merged PCI patches either.
> > 
> > So in short, this series has to go through the usual clock tree review
> > process.
> > 

I do know the normal procedure. But if patches concern different
subsystems but for some reason inter-depended somehow it's ok to merge
them in via a single repo. In my case the platform clock driver has
been updated in a way so to support the reset-controls utilized in the
PCIe driver altered in another patchset. So I didn't want to leave the
kernel not working in the framework of my platform on any git hash
state. That's why I asked to merge the patchsets in via the same repo.
The kernel would be still buildable though.

> 
> Yes, Stephen should be the one taking these patches through the clk tree. Also,
> there is no need to club both pci and clk patches in a single tree. That's
> usually done for patches with build dependencies, but here there are none.

Well, I didn't expect to have my patchsets review to be that delayed.
Now seeing Lorenzo is going to review only DW PCIe fixes and cleanups
after which will be gone for two more months I have to admit that my
plan of getting the changes accepted in 5.19 won't come true. Really
I thought of any subsystem but not of PCIe/DMA that review procedure
would last that long.

-Sergey

> 
> Thanks,
> Mani
> 
> > Thanks,
> > Lorenzo
> > 
> > > -Sergey
> > > 
> > > > 
> > > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > > > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > > > Cc: Rob Herring <robh@kernel.org>
> > > > Cc: "Krzysztof Wilczyński" <kw@linux.com>
> > > > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > > > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > > > Cc: linux-clk@vger.kernel.org
> > > > Cc: linux-pci@vger.kernel.org
> > > > Cc: linux-mips@vger.kernel.org
> > > > Cc: linux-kernel@vger.kernel.org
> > > > 
> > > > Serge Semin (4):
> > > >   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
> > > >   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
> > > >   clk: baikal-t1: Move reset-controls code into a dedicated module
> > > >   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> > > > 
> > > >  drivers/clk/baikal-t1/Kconfig       |  12 +-
> > > >  drivers/clk/baikal-t1/Makefile      |   1 +
> > > >  drivers/clk/baikal-t1/ccu-div.c     |   1 +
> > > >  drivers/clk/baikal-t1/ccu-div.h     |   6 +
> > > >  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
> > > >  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
> > > >  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
> > > >  include/dt-bindings/reset/bt1-ccu.h |   9 +
> > > >  8 files changed, 482 insertions(+), 86 deletions(-)
> > > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
> > > >  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> > > > 
> > > > -- 
> > > > 2.35.1
> > > > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Stephen Boyd]

Quoting Serge Semin (2022-05-12 14:14:31)
> On Thu, May 12, 2022 at 10:41:50PM +0530, Manivannan Sadhasivam wrote:
> > On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> > > So in short, this series has to go through the usual clock tree review
> > > process.
> > > 
> 
> I do know the normal procedure. But if patches concern different
> subsystems but for some reason inter-depended somehow it's ok to merge
> them in via a single repo. In my case the platform clock driver has
> been updated in a way so to support the reset-controls utilized in the
> PCIe driver altered in another patchset. So I didn't want to leave the
> kernel not working in the framework of my platform on any git hash
> state. That's why I asked to merge the patchsets in via the same repo.
> The kernel would be still buildable though.
> 

Is it going to be broken if I merge the clk patches through clk tree?
Has it ever worked? Does the kernel still boot, just PCIe fails if the
patches are applied?

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Serge Semin]

On Tue, May 17, 2022 at 12:40:18AM -0700, Stephen Boyd wrote:
> Quoting Serge Semin (2022-05-12 14:14:31)
> > On Thu, May 12, 2022 at 10:41:50PM +0530, Manivannan Sadhasivam wrote:
> > > On Thu, May 12, 2022 at 04:27:05PM +0100, Lorenzo Pieralisi wrote:
> > > > So in short, this series has to go through the usual clock tree review
> > > > process.
> > > > 
> > 
> > I do know the normal procedure. But if patches concern different
> > subsystems but for some reason inter-depended somehow it's ok to merge
> > them in via a single repo. In my case the platform clock driver has
> > been updated in a way so to support the reset-controls utilized in the
> > PCIe driver altered in another patchset. So I didn't want to leave the
> > kernel not working in the framework of my platform on any git hash
> > state. That's why I asked to merge the patchsets in via the same repo.
> > The kernel would be still buildable though.
> > 
> 

> Is it going to be broken if I merge the clk patches through clk tree?

No. It won't be broken.

> Has it ever worked?

It has and is working well except some minor fixes provided in this
petchset:
[PATCH v3 1/4] clk: baikal-t1: Fix invalid xGMAC PTP clock divider
[PATCH v3 2/4] clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent

> Does the kernel still boot, just PCIe fails if the
> patches are applied?

Yes, the kernel will be bootable. There won't be any problem if the patches
in this series are applied because it is self-consistent. As I
said in the cover letter there is an implicit dependency of another series
"[PATCH v2 00/17] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support"
(https://lore.kernel.org/linux-pci/20220503214638.1895-1-Sergey.Semin@baikalelectronics.ru/T/#me3c5c248adad9760702b545bd4bacd89d5f8a2bd)
from this one. In particular the functionality implemented in the
patch
"[PATCH v2 17/17] PCI: dwc: Add Baikal-T1 PCIe controller support"
(https://lore.kernel.org/linux-pci/20220503214638.1895-1-Sergey.Semin@baikalelectronics.ru/T/#m219e11c38c4ab8db0c2520c4050366d641598600)
depends on the patches 3 and 4 of this patchset. But the
dependency is implicit hidden under the DT clock/reset bindings layer.
The Baikal-T1 PCIe platform driver will just fail to probe the host
controller device if this series isn't applied. So the clock/reset
patchset can be freely merged in via the clk tree especially seeing
the PCIe Host/EP subsystem maintainer is going to be AFK from
Wednesday and my series will sadly but likely hang up in limbo for a
while.

-Sergey

Re: [PATCH v3 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

[Serge Semin]

Hello Stephen, Michael

The series has been here for about two months with no comments. Seeing
the dependent patches won't be merged in before the next merge window,
could you please merge this series in through your repo?

-Sergey

On Tue, May 03, 2022 at 11:57:18PM +0300, Serge Semin wrote:
> This patchset is an initial one in the series created in the framework
> of my Baikal-T1 PCIe/eDMA-related work:
> 
> [1: In-progress v3] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
> Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> [2: In-progress v1] PCI: dwc: Various fixes and cleanups
> Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> [3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
> Link: https://lore.kernel.org/linux-pci/20220324013734.18234-1-Sergey.Semin@baikalelectronics.ru/
> [4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
> Link: https://lore.kernel.org/linux-pci/20220324014836.19149-1-Sergey.Semin@baikalelectronics.ru/
> 
> Since some of the patches in the later patchsets depend on the
> modifications introduced here, @Lorenzo could you please merge this series
> through your PCIe subsystem repo? After getting all the required ack'es of
> course.
> 
> Short summary regarding this patchset. A few more modifications are
> introduced here to finally finish the Baikal-T1 CCU unit support up and
> prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
> all it turned out I specified wrong DW xGMAC PTP reference clock divider
> in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
> joint xGMAC Ref and PTP clock instead of having them separately defined.
> The SoC manual describes these clocks as separate fixed clock wrappers.
> Finally in order to close the SoC clock/reset support up we need to add
> the DDR and PCIe interfaces reset controls support. It's done in two
> steps. First I've moved the reset-controls-related code into a dedicated
> module. Then the DDR/PCIe reset-control functionality is added.
> 
> Link: https://lore.kernel.org/linux-pci/20220324010905.15589-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v2:
> - Resubmit the series with adding @Philipp to the list of the recipients.
> 
> Link: https://lore.kernel.org/linux-pci/20220330144320.27039-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v3:
> - Rebased from v5.17 onto v5.18-rc3.
> - No comments. Just resend the series.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Rob Herring <robh@kernel.org>
> Cc: "Krzysztof Wilczyński" <kw@linux.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: linux-clk@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: linux-mips@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> 
> Serge Semin (4):
>   clk: baikal-t1: Fix invalid xGMAC PTP clock divider
>   clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
>   clk: baikal-t1: Move reset-controls code into a dedicated module
>   clk: baikal-t1: Add DDR/PCIe directly controlled resets support
> 
>  drivers/clk/baikal-t1/Kconfig       |  12 +-
>  drivers/clk/baikal-t1/Makefile      |   1 +
>  drivers/clk/baikal-t1/ccu-div.c     |   1 +
>  drivers/clk/baikal-t1/ccu-div.h     |   6 +
>  drivers/clk/baikal-t1/ccu-rst.c     | 373 ++++++++++++++++++++++++++++
>  drivers/clk/baikal-t1/ccu-rst.h     |  64 +++++
>  drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
>  include/dt-bindings/reset/bt1-ccu.h |   9 +
>  8 files changed, 482 insertions(+), 86 deletions(-)
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
>  create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
> 
> -- 
> 2.35.1
>