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[192.154.179.37]) by smtp.gmail.com with ESMTPSA id c8-20020aca1c08000000b00326414c1bb7sm1030818oic.35.2022.05.26.14.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 14:29:32 -0700 (PDT) Received: (nullmailer pid 294758 invoked by uid 1000); Thu, 26 May 2022 21:29:30 -0000 Date: Thu, 26 May 2022 16:29:30 -0500 From: Rob Herring To: Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Serge Semin , Manivannan Sadhasivam , Alexey Malahov , Pavel Parkhomenko , Frank Li , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 02/13] PCI: dwc: Don't use generic IO-ops for DBI-space access Message-ID: <20220526212930.GN54904-robh@kernel.org> References: <20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru> <20220517125058.18488-3-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220517125058.18488-3-Sergey.Semin@baikalelectronics.ru> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, May 17, 2022 at 03:50:47PM +0300, Serge Semin wrote: > Commit c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") replaced > the locally defined DW PCIe host controller config-space accessors with > the generic methods pci_generic_config_read() and > pci_generic_config_write(). It was intended that the corresponding > bus-mapping callback returned a correct virtual address of the passed PCI > config-space register. The problem of the proposed solution was that it > didn't take into account the way the host config-space is accessed on the > DW PCIe. Depending on the DW PCIe IP-core synthesize parameters different > interfaces can be used to access the host and peripheral config/memory > spaces. The former one can be accessed via the DBI interface, while the > later ones is reached via the AHB/AXI application bus. In case if the DW > PCIe controller is configured to have a dedicated DBI interface, the way > it is mapped into the IO-memory turns to be platform-specific. For such > setups the DWC PCIe driver provides a set of the callbacks > dw_pcie_ops.{read_dbi,write_dbi} so the platforms glue-drivers would be > able to take into account the DBI bus IO peculiarities. Since > commit c2b0c098fbd1 ("PCI: dwc: Use generic config accessors") these > methods haven't been utilized during the generic host initialization > performed by the PCIe subsystem code. > > I don't really know how come there have been no problems spotted for the > Histb/Exynos/Kirin PCIe controllers so far, but in our case with dword Because they implement their own pci_ops for the root bus. You should too. Who is 'our case'? > aligned IO requirement the generic config-space accessors can't be > utilized for the host config-space. Thus in order to make sure the host > config-space is properly accessed via the DBI bus let's get back the > dw_pcie_rd_own_conf() and dw_pcie_wr_own_conf() methods. They are going to > be just wrappers around the already defined > dw_pcie_read_dbi()/dw_pcie_write_dbi() functions with proper arguments > conversion. These methods perform the platform-specific config-space IO if > the DBI accessors are specified, otherwise they call normal MMIO > operations. The idea was for DWC to not define its own way to have different read/write for root bus vs. child bus as many PCI host bridges need the same thing. So the host bridge struct now has 2 pci_ops pointers. And the mess of function pointer indirection is gone. Rob