From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stephen Boyd" <swboyd@chromium.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Taniya Das" <quic_tdas@quicinc.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: Johan Hovold <johan+linaro@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH v9 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling
Date: Fri, 3 Jun 2022 10:59:03 +0300 [thread overview]
Message-ID: <20220603075908.1853011-1-dmitry.baryshkov@linaro.org> (raw)
PCIe pipe clk (and some other clocks) must be parked to the "safe"
source (bi_tcxo) when corresponding GDSC is turned off and on again.
Currently this is handcoded in the PCIe driver by reparenting the
gcc_pipe_N_clk_src clock.
Instead of doing it manually, follow the approach used by
clk_rcg2_shared_ops and implement this parking in the enable() and
disable() clock operations for respective pipe clocks.
Changes since v8:
- Readded .name to changed entries in gcc-sc7280 driver to restore
compatibility with older DTS,
- Rebased on top of linux-next, dropping reverts,
- Verified to include all R-b tags (excuse me, Johan, I missed them
in the previous iteration).
Changes since v7:
- Brought back the struct clk_regmap_phy_mux (Johan)
- Fixed includes (Stephen)
- Dropped CLK_SET_RATE_PARENT flags from changed pipe clocks, they are
not set in the current code and they are useless as the PHY's clock
has fixed rate.
Changes since v6:
- Switched the ops to use GENMASK/FIELD_GET/FIELD_PUT (Stephen),
- As all pipe/symbol clock source clocks have the same register (and
parents) layout, hardcode all the values. If the need arises, this
can be changed later (Stephen),
- Fixed commit messages and comments (suggested by Johan),
- Added revert for the clk_regmap_mux_safe that have been already
picked up by Bjorn.
Changes since v5:
- Rename the clock to clk-regmap-phy-mux and the enable/disable values
to phy_src_val and ref_src_val respectively (as recommended by
Johan).
Changes since v4:
- Renamed the clock to clk-regmap-pipe-src,
- Added mention of PCIe2 PHY to the commit message,
- Expanded commit messages to mention additional pipe clock details.
Changes since v3:
- Replaced the clock multiplexer implementation with branch-like clock.
Changes since v2:
- Added is_enabled() callback
- Added default parent to the pipe clock configuration
Changes since v1:
- Rebased on top of [1].
- Removed erroneous Fixes tag from the patch 4.
Changes since RFC:
- Rework clk-regmap-mux fields. Specify safe parent as P_* value rather
than specifying the register value directly
- Expand commit message to the first patch to specially mention that
it is required only on newer generations of Qualcomm chipsets.
Dmitry Baryshkov (5):
clk: qcom: regmap: add PHY clock source implementation
clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe
clocks
clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe
clocks
PCI: qcom: Remove unnecessary pipe_clk handling
PCI: qcom: Drop manual pipe_clk_src handling
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-regmap-phy-mux.c | 62 ++++++++++++++++++++
drivers/clk/qcom/clk-regmap-phy-mux.h | 33 +++++++++++
drivers/clk/qcom/gcc-sc7280.c | 47 +++++----------
drivers/clk/qcom/gcc-sm8450.c | 49 +++++-----------
drivers/pci/controller/dwc/pcie-qcom.c | 81 +-------------------------
6 files changed, 125 insertions(+), 148 deletions(-)
create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c
create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h
--
2.35.1
Dmitry Baryshkov (5):
clk: qcom: regmap: add PHY clock source implementation
clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe
clocks
clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe
clocks
PCI: qcom: Remove unnecessary pipe_clk handling
PCI: qcom: Drop manual pipe_clk_src handling
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-regmap-phy-mux.c | 62 ++++++++++++++++++++
drivers/clk/qcom/clk-regmap-phy-mux.h | 33 +++++++++++
drivers/clk/qcom/gcc-sc7280.c | 47 +++++----------
drivers/clk/qcom/gcc-sm8450.c | 49 +++++-----------
drivers/pci/controller/dwc/pcie-qcom.c | 81 +-------------------------
6 files changed, 125 insertions(+), 148 deletions(-)
create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c
create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h
--
2.35.1
next reply other threads:[~2022-06-03 7:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-03 7:59 Dmitry Baryshkov [this message]
2022-06-03 7:59 ` [PATCH v9 1/5] clk: qcom: regmap: add PHY clock source implementation Dmitry Baryshkov
2022-06-03 7:59 ` [PATCH v9 2/5] clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks Dmitry Baryshkov
2022-06-03 8:17 ` Johan Hovold
2022-06-03 8:42 ` Dmitry Baryshkov
2022-06-03 8:50 ` Johan Hovold
2022-06-03 9:21 ` Dmitry Baryshkov
2022-06-03 7:59 ` [PATCH v9 3/5] clk: qcom: gcc-sc7280: " Dmitry Baryshkov
2022-06-03 7:59 ` [PATCH v9 4/5] PCI: qcom: Remove unnecessary pipe_clk handling Dmitry Baryshkov
2022-06-03 7:59 ` [PATCH v9 5/5] PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov
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