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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: "Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
	"Krzysztof Wilczyński" <kw@linux.com>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
	Frank Li <Frank.Li@nxp.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v3 08/15] PCI: dwc: Add host de-initialization callback
Date: Fri, 10 Jun 2022 11:44:36 +0300	[thread overview]
Message-ID: <20220610084444.14549-9-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru>

Seeing the platform-specific DW PCIe host-initialization is performed from
within the generic dw_pcie_host_init() method by means of the dedicated
dw_pcie_ops.host_init() callback, there must be declared an antagonist
which would perform the corresponding cleanups. Let's add such callback
then. It will be called in the dw_pcie_host_deinit() method and in the
cleanup-on-error path in the dw_pcie_host_init() function.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
 .../pci/controller/dwc/pcie-designware-host.c | 21 ++++++++++++++-----
 drivers/pci/controller/dwc/pcie-designware.h  |  1 +
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 0a1c475e7414..b9d251b86aaf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -354,13 +354,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 			pp->num_vectors = MSI_DEF_NUM_VECTORS;
 		} else if (pp->num_vectors > MAX_MSI_IRQS) {
 			dev_err(dev, "Invalid number of vectors\n");
-			return -EINVAL;
+			ret = -EINVAL;
+			goto err_deinit_host;
 		}
 
 		if (pp->ops->msi_host_init) {
 			ret = pp->ops->msi_host_init(pp);
 			if (ret < 0)
-				return ret;
+				goto err_deinit_host;
 		} else if (pp->has_msi_ctrl) {
 			u32 ctrl, num_ctrls;
 
@@ -372,8 +373,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 				pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
 				if (pp->msi_irq < 0) {
 					pp->msi_irq = platform_get_irq(pdev, 0);
-					if (pp->msi_irq < 0)
-						return pp->msi_irq;
+					if (pp->msi_irq < 0) {
+						ret = pp->msi_irq;
+						goto err_deinit_host;
+					}
 				}
 			}
 
@@ -381,7 +384,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 
 			ret = dw_pcie_allocate_domains(pp);
 			if (ret)
-				return ret;
+				goto err_deinit_host;
 
 			if (pp->msi_irq > 0)
 				irq_set_chained_handler_and_data(pp->msi_irq,
@@ -433,6 +436,11 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 err_free_msi:
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
+
+err_deinit_host:
+	if (pp->ops->host_deinit)
+		pp->ops->host_deinit(pp);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
@@ -448,6 +456,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
 
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
+
+	if (pp->ops->host_deinit)
+		pp->ops->host_deinit(pp);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d247f227464c..7f1c00fa084d 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -200,6 +200,7 @@ enum dw_pcie_device_mode {
 
 struct dw_pcie_host_ops {
 	int (*host_init)(struct dw_pcie_rp *pp);
+	void (*host_deinit)(struct dw_pcie_rp *pp);
 	int (*msi_host_init)(struct dw_pcie_rp *pp);
 };
 
-- 
2.35.1


  parent reply	other threads:[~2022-06-10  8:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-10  8:44 [PATCH v3 00/15] PCI: dwc: Add hw version and dma-ranges support Serge Semin
2022-06-10  8:44 ` [PATCH v3 01/15] PCI: dwc: Add more verbose link-up message Serge Semin
2022-06-10  8:44 ` [PATCH v3 02/15] PCI: dwc: Detect iATU settings after getting "addr_space" resource Serge Semin
2022-06-10  8:44 ` [PATCH v3 03/15] PCI: dwc: Convert to using native IP-core versions representation Serge Semin
2022-06-10  8:44 ` [PATCH v3 04/15] PCI: dwc: Add IP-core version detection procedure Serge Semin
2022-06-10  8:44 ` [PATCH v3 05/15] PCI: dwc: Introduce Synopsys IP-core versions/types interface Serge Semin
2022-06-10  8:44 ` [PATCH v3 06/15] PCI: intel-gw: Drop manual DW PCIe controller version setup Serge Semin
2022-06-10  8:44 ` [PATCH v3 07/15] PCI: tegra194: " Serge Semin
2022-06-10  8:44 ` Serge Semin [this message]
2022-06-10  8:44 ` [PATCH v3 09/15] PCI: dwc: Drop inbound iATU types enumeration - dw_pcie_as_type Serge Semin
2022-06-10  8:44 ` [PATCH v3 10/15] PCI: dwc: Drop iATU regions enumeration - dw_pcie_region_type Serge Semin
2022-06-10  8:44 ` [PATCH v3 11/15] PCI: dwc: Simplify in/outbound iATU setup methods Serge Semin
2022-06-10  8:44 ` [PATCH v3 12/15] PCI: dwc: Add iATU regions size detection procedure Serge Semin
2022-06-10  8:44 ` [PATCH v3 13/15] PCI: dwc: Verify in/out regions against iATU constraints Serge Semin
2022-06-10  8:44 ` [PATCH v3 14/15] PCI: dwc: Check iATU in/outbound ranges setup methods status Serge Semin
2022-06-10  8:44 ` [PATCH v3 15/15] PCI: dwc: Introduce dma-ranges property support for RC-host Serge Semin
2022-06-10  8:49 ` [PATCH v3 00/15] PCI: dwc: Add hw version and dma-ranges support Serge Semin

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