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* [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port
@ 2022-06-21 11:36 Bharat Kumar Gogada
  2022-06-21 11:36 ` [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
                   ` (2 more replies)
  0 siblings, 3 replies; 9+ messages in thread
From: Bharat Kumar Gogada @ 2022-06-21 11:36 UTC (permalink / raw)
  To: linux-pci, linux-kernel, devicetree
  Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
  to enable and handle legacy interrupts.

Changes in v5:
- Added of_device_get_match_data to identify CPM version.


Bharat Kumar Gogada (2):
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

 .../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
 drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
 2 files changed, 103 insertions(+), 7 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  2022-06-21 11:36 [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
@ 2022-06-21 11:36 ` Bharat Kumar Gogada
  2022-06-28 19:37   ` Rob Herring
  2022-06-21 11:36 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
  2022-06-21 22:28 ` [PATCH v5 0/2] Add support for Xilinx " Bjorn Helgaas
  2 siblings, 1 reply; 9+ messages in thread
From: Bharat Kumar Gogada @ 2022-06-21 11:36 UTC (permalink / raw)
  To: linux-pci, linux-kernel, devicetree
  Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada

Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.

Add support for YAML schemas documentation for Versal CPM5 Root Port driver.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index cca395317a4c..24ddc2855b94 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -14,17 +14,23 @@ allOf:
 
 properties:
   compatible:
-    const: xlnx,versal-cpm-host-1.00
+    enum:
+      - xlnx,versal-cpm-host-1.00
+      - xlnx,versal-cpm5-host
 
   reg:
     items:
       - description: CPM system level control and status registers.
       - description: Configuration space region and bridge registers.
+      - description: CPM5 control and status registers.
+    minItems: 2
 
   reg-names:
     items:
       - const: cpm_slcr
       - const: cfg
+      - const: cpm_csr
+    minItems: 2
 
   interrupts:
     maxItems: 1
@@ -95,4 +101,34 @@ examples:
                                interrupt-controller;
                        };
                };
+
+               cpm5_pcie: pcie@fcdd0000 {
+                       compatible = "xlnx,versal-cpm5-host";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       interrupts = <0 72 4>;
+                       interrupt-parent = <&gic>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
+                                       <0 0 0 2 &pcie_intc_1 1>,
+                                       <0 0 0 3 &pcie_intc_1 2>,
+                                       <0 0 0 4 &pcie_intc_1 3>;
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
+                       msi-map = <0x0 &its_gic 0x0 0x10000>;
+                       reg = <0x00 0xfcdd0000 0x00 0x1000>,
+                             <0x06 0x00000000 0x00 0x1000000>,
+                             <0x00 0xfce20000 0x00 0x1000000>;
+                       reg-names = "cpm_slcr", "cfg", "cpm_csr";
+
+                       pcie_intc_1: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
     };
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v5 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  2022-06-21 11:36 [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
  2022-06-21 11:36 ` [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
@ 2022-06-21 11:36 ` Bharat Kumar Gogada
  2022-06-21 22:28 ` [PATCH v5 0/2] Add support for Xilinx " Bjorn Helgaas
  2 siblings, 0 replies; 9+ messages in thread
From: Bharat Kumar Gogada @ 2022-06-21 11:36 UTC (permalink / raw)
  To: linux-pci, linux-kernel, devicetree
  Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
  to enable and handle legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++++++--
 1 file changed, 59 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index c7cd44ed4dfc..0bcd11d27eeb 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -35,6 +35,10 @@
 #define XILINX_CPM_PCIE_MISC_IR_ENABLE	0x00000348
 #define XILINX_CPM_PCIE_MISC_IR_LOCAL	BIT(1)
 
+#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0
+#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8
+#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)
+
 /* Interrupt registers definitions */
 #define XILINX_CPM_PCIE_INTR_LINK_DOWN		0
 #define XILINX_CPM_PCIE_INTR_HOT_RESET		3
@@ -98,6 +102,16 @@
 /* Phy Status/Control Register definitions */
 #define XILINX_CPM_PCIE_REG_PSCR_LNKUP		BIT(11)
 
+/**
+ * struct xilinx_cpm_variant - CPM variant information
+ * @cpm_version: CPM5 has few changes compared to CPM block.
+ *      CPM5 has dedicated register space for control and status registers.
+ *
+ */
+struct xilinx_cpm_variant {
+	bool cpm_version;
+};
+
 /**
  * struct xilinx_cpm_pcie - PCIe port information
  * @dev: Device pointer
@@ -109,6 +123,7 @@
  * @intx_irq: legacy interrupt number
  * @irq: Error interrupt number
  * @lock: lock protecting shared register access
+ * @is_cpm5: value to check cpm version
  */
 struct xilinx_cpm_pcie {
 	struct device			*dev;
@@ -120,6 +135,7 @@ struct xilinx_cpm_pcie {
 	int				intx_irq;
 	int				irq;
 	raw_spinlock_t			lock;
+	bool                            is_cpm5;
 };
 
 static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
@@ -285,6 +301,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
 		generic_handle_domain_irq(port->cpm_domain, i);
 	pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
 
+	if (port->is_cpm5) {
+		val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
+		if (val)
+			writel_relaxed(val,
+				       port->cpm_base +
+				       XILINX_CPM_PCIE_IR_STATUS);
+	}
+
 	/*
 	 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
 	 * CPM SLCR block.
@@ -484,6 +508,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
 	 */
 	writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
 	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
+
+	if (port->is_cpm5) {
+		writel(XILINX_CPM_PCIE_IR_LOCAL,
+		       port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
+	}
+
 	/* Enable the Bridge enable bit */
 	pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
 		   XILINX_CPM_PCIE_REG_RPSC_BEN,
@@ -503,6 +533,10 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
 	struct device *dev = port->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct resource *res;
+	const struct xilinx_cpm_variant *variant =
+		of_device_get_match_data(dev);
+
+	port->is_cpm5 = variant->cpm_version;
 
 	port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
 							       "cpm_slcr");
@@ -518,7 +552,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
 	if (IS_ERR(port->cfg))
 		return PTR_ERR(port->cfg);
 
-	port->reg_base = port->cfg->win;
+	if (port->is_cpm5) {
+		port->reg_base = devm_platform_ioremap_resource_byname(pdev,
+								       "cpm_csr");
+		if (IS_ERR(port->reg_base))
+			return PTR_ERR(port->reg_base);
+	} else {
+		port->reg_base = port->cfg->win;
+	}
 
 	return 0;
 }
@@ -591,9 +632,24 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 	return err;
 }
 
+static const struct xilinx_cpm_variant cpm_host = {
+	.cpm_version = false,
+};
+
+static const struct xilinx_cpm_variant cpm5_host = {
+	.cpm_version = true,
+};
+
 static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
-	{ .compatible = "xlnx,versal-cpm-host-1.00", },
-	{}
+	{
+		.compatible = "xlnx,versal-cpm-host-1.00",
+		.data = &cpm_host,
+	},
+	{
+		.compatible = "xlnx,versal-cpm5-host",
+		.data = &cpm5_host,
+	},
+	{},
 };
 
 static struct platform_driver xilinx_cpm_pcie_driver = {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port
  2022-06-21 11:36 [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
  2022-06-21 11:36 ` [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
  2022-06-21 11:36 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
@ 2022-06-21 22:28 ` Bjorn Helgaas
  2 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2022-06-21 22:28 UTC (permalink / raw)
  To: Bharat Kumar Gogada
  Cc: linux-pci, linux-kernel, devicetree, lorenzo.pieralisi, bhelgaas,
	michals, robh

On Tue, Jun 21, 2022 at 05:06:51PM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
> 
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additonal register bit
>   to enable and handle legacy interrupts.
> 
> Changes in v5:
> - Added of_device_get_match_data to identify CPM version.
> 
> 
> Bharat Kumar Gogada (2):
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> 
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
>  drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
>  2 files changed, 103 insertions(+), 7 deletions(-)

This is the third "v5" posting:

  #1 Jun 16 https://lore.kernel.org/r/20220616124429.12917-1-bharat.kumar.gogada@xilinx.com
  #2 Jun 18 https://lore.kernel.org/r/20220618024459.7554-1-bharat.kumar.gogada@xilinx.com
  #3 Jun 21 https://lore.kernel.org/r/20220621113653.2354462-1-bharat.kumar.gogada@xilinx.com

This makes things harder than necessary.

I commented on a couple things in #2, and you said you were going to
fix them, but they aren't fixed in #3.

It will also make things easier if you include the MAINTAINERS patch
in the same series.  There's no reason for it to be separate.

Can you please post a v6 with the updates?

Bjorn

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  2022-06-21 11:36 ` [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
@ 2022-06-28 19:37   ` Rob Herring
  0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-06-28 19:37 UTC (permalink / raw)
  To: Bharat Kumar Gogada
  Cc: linux-kernel, michals, bhelgaas, devicetree, linux-pci,
	lorenzo.pieralisi

On Tue, 21 Jun 2022 17:06:52 +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functionality at Gen5 speed.
> 
> Add support for YAML schemas documentation for Versal CPM5 Root Port driver.
> 
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++++++++++-
>  1 file changed, 37 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  2022-06-18  2:44 Bharat Kumar Gogada
@ 2022-06-18  2:44 ` Bharat Kumar Gogada
  0 siblings, 0 replies; 9+ messages in thread
From: Bharat Kumar Gogada @ 2022-06-18  2:44 UTC (permalink / raw)
  To: linux-pci, linux-kernel, devicetree
  Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
  to enable and handle legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++++++--
 1 file changed, 59 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index c7cd44ed4dfc..0bcd11d27eeb 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -35,6 +35,10 @@
 #define XILINX_CPM_PCIE_MISC_IR_ENABLE	0x00000348
 #define XILINX_CPM_PCIE_MISC_IR_LOCAL	BIT(1)
 
+#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0
+#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8
+#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)
+
 /* Interrupt registers definitions */
 #define XILINX_CPM_PCIE_INTR_LINK_DOWN		0
 #define XILINX_CPM_PCIE_INTR_HOT_RESET		3
@@ -98,6 +102,16 @@
 /* Phy Status/Control Register definitions */
 #define XILINX_CPM_PCIE_REG_PSCR_LNKUP		BIT(11)
 
+/**
+ * struct xilinx_cpm_variant - CPM variant information
+ * @cpm_version: CPM5 has few changes compared to CPM block.
+ *      CPM5 has dedicated register space for control and status registers.
+ *
+ */
+struct xilinx_cpm_variant {
+	bool cpm_version;
+};
+
 /**
  * struct xilinx_cpm_pcie - PCIe port information
  * @dev: Device pointer
@@ -109,6 +123,7 @@
  * @intx_irq: legacy interrupt number
  * @irq: Error interrupt number
  * @lock: lock protecting shared register access
+ * @is_cpm5: value to check cpm version
  */
 struct xilinx_cpm_pcie {
 	struct device			*dev;
@@ -120,6 +135,7 @@ struct xilinx_cpm_pcie {
 	int				intx_irq;
 	int				irq;
 	raw_spinlock_t			lock;
+	bool                            is_cpm5;
 };
 
 static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
@@ -285,6 +301,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
 		generic_handle_domain_irq(port->cpm_domain, i);
 	pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
 
+	if (port->is_cpm5) {
+		val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
+		if (val)
+			writel_relaxed(val,
+				       port->cpm_base +
+				       XILINX_CPM_PCIE_IR_STATUS);
+	}
+
 	/*
 	 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
 	 * CPM SLCR block.
@@ -484,6 +508,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
 	 */
 	writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
 	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
+
+	if (port->is_cpm5) {
+		writel(XILINX_CPM_PCIE_IR_LOCAL,
+		       port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
+	}
+
 	/* Enable the Bridge enable bit */
 	pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
 		   XILINX_CPM_PCIE_REG_RPSC_BEN,
@@ -503,6 +533,10 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
 	struct device *dev = port->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct resource *res;
+	const struct xilinx_cpm_variant *variant =
+		of_device_get_match_data(dev);
+
+	port->is_cpm5 = variant->cpm_version;
 
 	port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
 							       "cpm_slcr");
@@ -518,7 +552,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
 	if (IS_ERR(port->cfg))
 		return PTR_ERR(port->cfg);
 
-	port->reg_base = port->cfg->win;
+	if (port->is_cpm5) {
+		port->reg_base = devm_platform_ioremap_resource_byname(pdev,
+								       "cpm_csr");
+		if (IS_ERR(port->reg_base))
+			return PTR_ERR(port->reg_base);
+	} else {
+		port->reg_base = port->cfg->win;
+	}
 
 	return 0;
 }
@@ -591,9 +632,24 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 	return err;
 }
 
+static const struct xilinx_cpm_variant cpm_host = {
+	.cpm_version = false,
+};
+
+static const struct xilinx_cpm_variant cpm5_host = {
+	.cpm_version = true,
+};
+
 static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
-	{ .compatible = "xlnx,versal-cpm-host-1.00", },
-	{}
+	{
+		.compatible = "xlnx,versal-cpm-host-1.00",
+		.data = &cpm_host,
+	},
+	{
+		.compatible = "xlnx,versal-cpm5-host",
+		.data = &cpm5_host,
+	},
+	{},
 };
 
 static struct platform_driver xilinx_cpm_pcie_driver = {
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* RE: [PATCH v5 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  2022-06-16 19:19   ` Bjorn Helgaas
@ 2022-06-18  2:36     ` Gogada, Bharat Kumar
  0 siblings, 0 replies; 9+ messages in thread
From: Gogada, Bharat Kumar @ 2022-06-18  2:36 UTC (permalink / raw)
  To: Bjorn Helgaas, Bharat Kumar Gogada
  Cc: linux-pci, linux-kernel, devicetree, lorenzo.pieralisi, bhelgaas,
	michals, robh

> 
> On Thu, Jun 16, 2022 at 06:14:29PM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root Port
> > functioning at Gen5 speed.
> >
> > Xilinx Versal CPM5 has few changes with existing CPM block.
> > - CPM5 has dedicated register space for control and status registers.
> > - CPM5 legacy interrupt handling needs additional register bit
> >   to enable and handle legacy interrupts.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> >  drivers/pci/controller/pcie-xilinx-cpm.c | 62
> > ++++++++++++++++++++++--
> >  1 file changed, 59 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> > b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index c7cd44ed4dfc..0bcd11d27eeb 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -35,6 +35,10 @@
> >  #define XILINX_CPM_PCIE_MISC_IR_ENABLE       0x00000348
> >  #define XILINX_CPM_PCIE_MISC_IR_LOCAL        BIT(1)
> >
> > +#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0
> > +#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8
> > +#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)
> > +
> >  /* Interrupt registers definitions */
> >  #define XILINX_CPM_PCIE_INTR_LINK_DOWN               0
> >  #define XILINX_CPM_PCIE_INTR_HOT_RESET               3
> > @@ -98,6 +102,16 @@
> >  /* Phy Status/Control Register definitions */
> >  #define XILINX_CPM_PCIE_REG_PSCR_LNKUP               BIT(11)
> >
> > +/**
> > + * struct xilinx_cpm_variant - CPM variant information
> > + * @cpm_version: CPM5 has few changes compared to CPM block.
> > + *      CPM5 has dedicated register space for control and status registers.
> > + *
> 
> Superfluous blank line.
> 
> > + */
> > +struct xilinx_cpm_variant {
> > +     bool cpm_version;
> 
> This is not really a bool, unless you want to preclude the possibility of ever
> having a CPM6 or other future variants.
> 
> > +};
> > +
> >  /**
> >   * struct xilinx_cpm_pcie - PCIe port information
> >   * @dev: Device pointer
> > @@ -109,6 +123,7 @@
> >   * @intx_irq: legacy interrupt number
> >   * @irq: Error interrupt number
> >   * @lock: lock protecting shared register access
> > + * @is_cpm5: value to check cpm version
> >   */
> >  struct xilinx_cpm_pcie {
> >       struct device                   *dev;
> > @@ -120,6 +135,7 @@ struct xilinx_cpm_pcie {
> >       int                             intx_irq;
> >       int                             irq;
> >       raw_spinlock_t                  lock;
> > +     bool                            is_cpm5;
> >  };
> >
> >  static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) @@ -285,6
> > +301,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
> >               generic_handle_domain_irq(port->cpm_domain, i);
> >       pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
> >
> > +     if (port->is_cpm5) {
> > +             val = readl_relaxed(port->cpm_base +
> XILINX_CPM_PCIE_IR_STATUS);
> > +             if (val)
> > +                     writel_relaxed(val,
> > +                                    port->cpm_base +
> > +                                    XILINX_CPM_PCIE_IR_STATUS);
> > +     }
> > +
> >       /*
> >        * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
> >        * CPM SLCR block.
> > @@ -484,6 +508,12 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
> >        */
> >       writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
> >              port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> > +
> > +     if (port->is_cpm5) {
> > +             writel(XILINX_CPM_PCIE_IR_LOCAL,
> > +                    port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
> > +     }
> > +
> >       /* Enable the Bridge enable bit */
> >       pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
> >                  XILINX_CPM_PCIE_REG_RPSC_BEN, @@ -503,6 +533,10 @@
> > static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
> >       struct device *dev = port->dev;
> >       struct platform_device *pdev = to_platform_device(dev);
> >       struct resource *res;
> > +     const struct xilinx_cpm_variant *variant =
> > +             of_device_get_match_data(dev);
> > +
> > +     port->is_cpm5 = variant->cpm_version;
> 
> It's a little clunky to use booleans for a potentially multi-valued version and
> to copy them around.  Something like this might leave room for future
> variants that need more knobs:

Agreed will fix this in next patch.

Regards,
Bharat

>   enum xilinx_cpm_version {
>     CPM,
>     CPM5,
>   };
> 
>   struct xilinx_cpm_variant {
>     enum xilinx_cpm_version version;
>   };
> 
>   struct xilinx_cpm_pcie {
>     ...
>     const struct xilinx_cpm_variant   *variant;
> 
>   static const struct xilinx_cpm_variant cpm5 = {
>     .version = CPM5,
>   };
> 
>   xilinx_cpm_pcie_event_flow()
>   {
>     ...
>     if (port->variant->version == CPM5)
> 
>   xilinx_cpm_pcie_probe()
>   {
>     ...
>     port->variant = of_device_get_match_data(dev);
> 
> 
> >       port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
> >
> > "cpm_slcr"); @@ -518,7 +552,14 @@ static int
> xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
> >       if (IS_ERR(port->cfg))
> >               return PTR_ERR(port->cfg);
> >
> > -     port->reg_base = port->cfg->win;
> > +     if (port->is_cpm5) {
> > +             port->reg_base =
> devm_platform_ioremap_resource_byname(pdev,
> > +                                                                    "cpm_csr");
> > +             if (IS_ERR(port->reg_base))
> > +                     return PTR_ERR(port->reg_base);
> > +     } else {
> > +             port->reg_base = port->cfg->win;
> > +     }
> >
> >       return 0;
> >  }
> > @@ -591,9 +632,24 @@ static int xilinx_cpm_pcie_probe(struct
> platform_device *pdev)
> >       return err;
> >  }
> >
> > +static const struct xilinx_cpm_variant cpm_host = {
> > +     .cpm_version = false,
> > +};
> > +
> > +static const struct xilinx_cpm_variant cpm5_host = {
> > +     .cpm_version = true,
> > +};
> > +
> >  static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
> > -     { .compatible = "xlnx,versal-cpm-host-1.00", },
> > -     {}
> > +     {
> > +             .compatible = "xlnx,versal-cpm-host-1.00",
> > +             .data = &cpm_host,
> > +     },
> > +     {
> > +             .compatible = "xlnx,versal-cpm5-host",
> > +             .data = &cpm5_host,
> > +     },
> > +     {},
> >  };
> >
> >  static struct platform_driver xilinx_cpm_pcie_driver = {
> > --
> > 2.17.1
> >

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  2022-06-16 12:44 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
@ 2022-06-16 19:19   ` Bjorn Helgaas
  2022-06-18  2:36     ` Gogada, Bharat Kumar
  0 siblings, 1 reply; 9+ messages in thread
From: Bjorn Helgaas @ 2022-06-16 19:19 UTC (permalink / raw)
  To: Bharat Kumar Gogada
  Cc: linux-pci, linux-kernel, devicetree, lorenzo.pieralisi, bhelgaas,
	michals, robh

On Thu, Jun 16, 2022 at 06:14:29PM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
> 
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
>   to enable and handle legacy interrupts.
> 
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> ---
>  drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++++++--
>  1 file changed, 59 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
> index c7cd44ed4dfc..0bcd11d27eeb 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -35,6 +35,10 @@
>  #define XILINX_CPM_PCIE_MISC_IR_ENABLE	0x00000348
>  #define XILINX_CPM_PCIE_MISC_IR_LOCAL	BIT(1)
>  
> +#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0
> +#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8
> +#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)
> +
>  /* Interrupt registers definitions */
>  #define XILINX_CPM_PCIE_INTR_LINK_DOWN		0
>  #define XILINX_CPM_PCIE_INTR_HOT_RESET		3
> @@ -98,6 +102,16 @@
>  /* Phy Status/Control Register definitions */
>  #define XILINX_CPM_PCIE_REG_PSCR_LNKUP		BIT(11)
>  
> +/**
> + * struct xilinx_cpm_variant - CPM variant information
> + * @cpm_version: CPM5 has few changes compared to CPM block.
> + *      CPM5 has dedicated register space for control and status registers.
> + *

Superfluous blank line.

> + */
> +struct xilinx_cpm_variant {
> +	bool cpm_version;

This is not really a bool, unless you want to preclude the possibility
of ever having a CPM6 or other future variants.

> +};
> +
>  /**
>   * struct xilinx_cpm_pcie - PCIe port information
>   * @dev: Device pointer
> @@ -109,6 +123,7 @@
>   * @intx_irq: legacy interrupt number
>   * @irq: Error interrupt number
>   * @lock: lock protecting shared register access
> + * @is_cpm5: value to check cpm version
>   */
>  struct xilinx_cpm_pcie {
>  	struct device			*dev;
> @@ -120,6 +135,7 @@ struct xilinx_cpm_pcie {
>  	int				intx_irq;
>  	int				irq;
>  	raw_spinlock_t			lock;
> +	bool                            is_cpm5;
>  };
>  
>  static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
> @@ -285,6 +301,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
>  		generic_handle_domain_irq(port->cpm_domain, i);
>  	pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
>  
> +	if (port->is_cpm5) {
> +		val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
> +		if (val)
> +			writel_relaxed(val,
> +				       port->cpm_base +
> +				       XILINX_CPM_PCIE_IR_STATUS);
> +	}
> +
>  	/*
>  	 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
>  	 * CPM SLCR block.
> @@ -484,6 +508,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
>  	 */
>  	writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
>  	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> +
> +	if (port->is_cpm5) {
> +		writel(XILINX_CPM_PCIE_IR_LOCAL,
> +		       port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
> +	}
> +
>  	/* Enable the Bridge enable bit */
>  	pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
>  		   XILINX_CPM_PCIE_REG_RPSC_BEN,
> @@ -503,6 +533,10 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
>  	struct device *dev = port->dev;
>  	struct platform_device *pdev = to_platform_device(dev);
>  	struct resource *res;
> +	const struct xilinx_cpm_variant *variant =
> +		of_device_get_match_data(dev);
> +
> +	port->is_cpm5 = variant->cpm_version;

It's a little clunky to use booleans for a potentially multi-valued
version and to copy them around.  Something like this might leave room
for future variants that need more knobs:

  enum xilinx_cpm_version {
    CPM,
    CPM5,
  };

  struct xilinx_cpm_variant {
    enum xilinx_cpm_version version;
  };

  struct xilinx_cpm_pcie {
    ...
    const struct xilinx_cpm_variant   *variant;

  static const struct xilinx_cpm_variant cpm5 = {
    .version = CPM5,
  };

  xilinx_cpm_pcie_event_flow()
  {
    ...
    if (port->variant->version == CPM5)

  xilinx_cpm_pcie_probe()
  {
    ...
    port->variant = of_device_get_match_data(dev);


>  	port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
>  							       "cpm_slcr");
> @@ -518,7 +552,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
>  	if (IS_ERR(port->cfg))
>  		return PTR_ERR(port->cfg);
>  
> -	port->reg_base = port->cfg->win;
> +	if (port->is_cpm5) {
> +		port->reg_base = devm_platform_ioremap_resource_byname(pdev,
> +								       "cpm_csr");
> +		if (IS_ERR(port->reg_base))
> +			return PTR_ERR(port->reg_base);
> +	} else {
> +		port->reg_base = port->cfg->win;
> +	}
>  
>  	return 0;
>  }
> @@ -591,9 +632,24 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
>  	return err;
>  }
>  
> +static const struct xilinx_cpm_variant cpm_host = {
> +	.cpm_version = false,
> +};
> +
> +static const struct xilinx_cpm_variant cpm5_host = {
> +	.cpm_version = true,
> +};
> +
>  static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
> -	{ .compatible = "xlnx,versal-cpm-host-1.00", },
> -	{}
> +	{
> +		.compatible = "xlnx,versal-cpm-host-1.00",
> +		.data = &cpm_host,
> +	},
> +	{
> +		.compatible = "xlnx,versal-cpm5-host",
> +		.data = &cpm5_host,
> +	},
> +	{},
>  };
>  
>  static struct platform_driver xilinx_cpm_pcie_driver = {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v5 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  2022-06-16 12:44 [PATCH v5 0/2] Add support for Xilinx " Bharat Kumar Gogada
@ 2022-06-16 12:44 ` Bharat Kumar Gogada
  2022-06-16 19:19   ` Bjorn Helgaas
  0 siblings, 1 reply; 9+ messages in thread
From: Bharat Kumar Gogada @ 2022-06-16 12:44 UTC (permalink / raw)
  To: linux-pci, linux-kernel, devicetree
  Cc: lorenzo.pieralisi, bhelgaas, michals, robh, Bharat Kumar Gogada

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
  to enable and handle legacy interrupts.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++++++--
 1 file changed, 59 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index c7cd44ed4dfc..0bcd11d27eeb 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -35,6 +35,10 @@
 #define XILINX_CPM_PCIE_MISC_IR_ENABLE	0x00000348
 #define XILINX_CPM_PCIE_MISC_IR_LOCAL	BIT(1)
 
+#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0
+#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8
+#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)
+
 /* Interrupt registers definitions */
 #define XILINX_CPM_PCIE_INTR_LINK_DOWN		0
 #define XILINX_CPM_PCIE_INTR_HOT_RESET		3
@@ -98,6 +102,16 @@
 /* Phy Status/Control Register definitions */
 #define XILINX_CPM_PCIE_REG_PSCR_LNKUP		BIT(11)
 
+/**
+ * struct xilinx_cpm_variant - CPM variant information
+ * @cpm_version: CPM5 has few changes compared to CPM block.
+ *      CPM5 has dedicated register space for control and status registers.
+ *
+ */
+struct xilinx_cpm_variant {
+	bool cpm_version;
+};
+
 /**
  * struct xilinx_cpm_pcie - PCIe port information
  * @dev: Device pointer
@@ -109,6 +123,7 @@
  * @intx_irq: legacy interrupt number
  * @irq: Error interrupt number
  * @lock: lock protecting shared register access
+ * @is_cpm5: value to check cpm version
  */
 struct xilinx_cpm_pcie {
 	struct device			*dev;
@@ -120,6 +135,7 @@ struct xilinx_cpm_pcie {
 	int				intx_irq;
 	int				irq;
 	raw_spinlock_t			lock;
+	bool                            is_cpm5;
 };
 
 static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
@@ -285,6 +301,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
 		generic_handle_domain_irq(port->cpm_domain, i);
 	pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
 
+	if (port->is_cpm5) {
+		val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
+		if (val)
+			writel_relaxed(val,
+				       port->cpm_base +
+				       XILINX_CPM_PCIE_IR_STATUS);
+	}
+
 	/*
 	 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
 	 * CPM SLCR block.
@@ -484,6 +508,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
 	 */
 	writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
 	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
+
+	if (port->is_cpm5) {
+		writel(XILINX_CPM_PCIE_IR_LOCAL,
+		       port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
+	}
+
 	/* Enable the Bridge enable bit */
 	pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
 		   XILINX_CPM_PCIE_REG_RPSC_BEN,
@@ -503,6 +533,10 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
 	struct device *dev = port->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct resource *res;
+	const struct xilinx_cpm_variant *variant =
+		of_device_get_match_data(dev);
+
+	port->is_cpm5 = variant->cpm_version;
 
 	port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
 							       "cpm_slcr");
@@ -518,7 +552,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
 	if (IS_ERR(port->cfg))
 		return PTR_ERR(port->cfg);
 
-	port->reg_base = port->cfg->win;
+	if (port->is_cpm5) {
+		port->reg_base = devm_platform_ioremap_resource_byname(pdev,
+								       "cpm_csr");
+		if (IS_ERR(port->reg_base))
+			return PTR_ERR(port->reg_base);
+	} else {
+		port->reg_base = port->cfg->win;
+	}
 
 	return 0;
 }
@@ -591,9 +632,24 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 	return err;
 }
 
+static const struct xilinx_cpm_variant cpm_host = {
+	.cpm_version = false,
+};
+
+static const struct xilinx_cpm_variant cpm5_host = {
+	.cpm_version = true,
+};
+
 static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
-	{ .compatible = "xlnx,versal-cpm-host-1.00", },
-	{}
+	{
+		.compatible = "xlnx,versal-cpm-host-1.00",
+		.data = &cpm_host,
+	},
+	{
+		.compatible = "xlnx,versal-cpm5-host",
+		.data = &cpm5_host,
+	},
+	{},
 };
 
 static struct platform_driver xilinx_cpm_pcie_driver = {
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-06-28 19:44 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-21 11:36 [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
2022-06-21 11:36 ` [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
2022-06-28 19:37   ` Rob Herring
2022-06-21 11:36 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
2022-06-21 22:28 ` [PATCH v5 0/2] Add support for Xilinx " Bjorn Helgaas
  -- strict thread matches above, loose matches on Subject: below --
2022-06-18  2:44 Bharat Kumar Gogada
2022-06-18  2:44 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
2022-06-16 12:44 [PATCH v5 0/2] Add support for Xilinx " Bharat Kumar Gogada
2022-06-16 12:44 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
2022-06-16 19:19   ` Bjorn Helgaas
2022-06-18  2:36     ` Gogada, Bharat Kumar

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