From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20528C43334 for ; Fri, 24 Jun 2022 17:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231922AbiFXRLR (ORCPT ); Fri, 24 Jun 2022 13:11:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229969AbiFXRLQ (ORCPT ); Fri, 24 Jun 2022 13:11:16 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01602522CB; Fri, 24 Jun 2022 10:11:15 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A8437B82AD2; Fri, 24 Jun 2022 17:11:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32448C34114; Fri, 24 Jun 2022 17:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656090673; bh=D4lolD9AmX1X3qRrzPxA81y4WM5Ett/5C8PadMrGeuM=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=FmpLm8M97dO7waV33x83kLNE4i9x4eMGvpGfYRgoD9WF28TPSAIW4vo2DdWq4+/90 NHUTMIjfd1104CN+zSztDYHFxWPUlONCtUYyB1qxrbnIMgADhYDjjYGzfgm8t4GB0f Bniut/HbPAZ7pk7noSboHdG+yyJgph35kviu65bXPMeaj42Ei0rAZjDThtkFyUxEdc gYSEX5PO0OywTeWH0GcClrRes6FIDptN/6Y/pNfqtaDAVz1MkHBylNcga8Qnsy65kK +/dZvYWJuH6Lh46HaN8vKxPCdRUopRBfH28q6Fc59uRHMLHgAyM9fTxMIuwiq97vXv 1BxfDWKHGXUQQ== Date: Fri, 24 Jun 2022 12:11:11 -0500 From: Bjorn Helgaas To: Krishna chaitanya chundru Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas Subject: Re: [PATCH v2] PCI: qcom: Allow L1 and its sub states Message-ID: <20220624171111.GA1542083@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1655298939-392-1-git-send-email-quic_krichai@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Jun 15, 2022 at 06:45:39PM +0530, Krishna chaitanya chundru wrote: > Allow L1 and its sub-states in the qcom pcie driver. > By default this is disabled in the hardware. So enabling it explicitly. > > Signed-off-by: Krishna chaitanya chundru I have a vague memory of my questions at [1] being answered, but I don't see the answers on the mailing list. Maybe I missed it? We should expand the commit log a bit with those details. I'm also hoping for an ack from Stanimir, Andy, or Bjorn A., since they're listed as maintainers of this driver. [1] https://lore.kernel.org/r/20220615154422.GA941075@bhelgaas > --- > drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 6ab9089..0d8efcc 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -41,6 +41,9 @@ > #define L23_CLK_RMV_DIS BIT(2) > #define L1_CLK_RMV_DIS BIT(1) > > +#define PCIE20_PARF_PM_CTRL 0x20 > +#define REQ_NOT_ENTR_L1 BIT(5) > + > #define PCIE20_PARF_PHY_CTRL 0x40 > #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) > #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) > @@ -1267,6 +1270,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val |= BIT(4); > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > + /* Enable L1 and L1ss */ > + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); > + val &= ~REQ_NOT_ENTR_L1; > + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); > + > if (IS_ENABLED(CONFIG_PCI_MSI)) { > val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > val |= BIT(31); > -- > 2.7.4 >