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From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
	bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be,
	magnus.damm@gmail.com
Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v2 06/13] PCI: dwc: host: Read num-lanes property before host_init()
Date: Mon, 27 Jun 2022 21:24:10 +0900	[thread overview]
Message-ID: <20220627122417.809615-7-yoshihiro.shimoda.uh@renesas.com> (raw)
In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com>

Vendor-specific initialization needs this information so that
read it before host_init(). And then, we can assume that
dw_pcie_{ep,host}_init() gets the property so that dw_pcie_setup()
doesn't need to get it again.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 2 ++
 drivers/pci/controller/dwc/pcie-designware.c      | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 1e3972c487b5..cf875bdcfabb 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -336,6 +336,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	if (pci->link_gen < 1)
 		pci->link_gen = of_pci_get_max_link_speed(np);
 
+	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
+
 	/* Set default bus ops */
 	bridge->ops = &dw_pcie_ops;
 	bridge->child_ops = &dw_child_pcie_ops;
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index d92c8a25094f..101e892e22e8 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -726,7 +726,6 @@ void dw_pcie_setup(struct dw_pcie *pci)
 	val |= PORT_LINK_DLL_LINK_EN;
 	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 
-	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
 	if (!pci->num_lanes) {
 		dev_dbg(pci->dev, "Using h/w default number of lanes\n");
 		return;
-- 
2.25.1


  parent reply	other threads:[~2022-06-27 12:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-27 12:24 [PATCH v2 00/13] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 01/13] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 02/13] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 03/13] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 04/13] PCI: dwc: Add reset_all_bars flag Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 05/13] PCI: dwc: endpoint: Read num-lanes property before ep_pre_init() Yoshihiro Shimoda
2022-06-27 12:24 ` Yoshihiro Shimoda [this message]
2022-06-27 12:24 ` [PATCH v2 07/13] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 08/13] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 09/13] PCI: renesas: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
2022-06-28  7:45   ` Geert Uytterhoeven
2022-06-28 12:24     ` Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 10/13] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2022-06-28  7:50   ` Geert Uytterhoeven
2022-06-28 12:33     ` Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 11/13] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 12/13] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2022-06-27 12:24 ` [PATCH v2 13/13] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda

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