[PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[Serge Semin]

This patchset is a first one in the series created in the framework of
my Baikal-T1 PCIe/eDMA-related work:

[1: In-progress v5] PCI: dwc: Various fixes and cleanups
Link: ---you are looking at it---
[2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support
Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru/
[3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support
Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru/
[4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support
Link: https://lore.kernel.org/linux-pci/20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru/

Note it is very recommended to merge the patchsets in the same order as
they are placed in the list above in order to prevent possible merge
conflicts. Nothing prevents them from being reviewed synchronously though.
Any tests are very welcome!

As it can be easily inferred from the patchset title, this series is about
the DW PCIe Root Port/Endpoint driver fixes and the code cleanups, where
fixes come before the cleanup patches. The patchset starts with adding the
stop_link() platform-specific method invocation in case of the PCIe host
probe procedure errors. It has been missing in the cleanup-on-error path
of the DW PCIe Host initialization method. After that the unrolled CSRs
layout is added to the iATU disable procedure. In third the disable iATU
procedure is fixed to be called only for the internal ATU as being
specific for the internal ATU implementation. Then the outbound iATU
extended region setup procedure is fixed to have the INCREASE_REGION_SIZE
flag set based on the limit-address - not the region size one. The last
but not least the CDM-check enabling procedure is fixed to be independent
from the non-related num_lanes field state.

Afterwards there is a series of cleanups. It concerns the changes like
adding braces to the multi-line if-else constructions, trailing new-lines
to the print format-string, dropping unnecessary version checking, and
various code simplifications and optimizations.

New features like adding two-level DT bindings abstraction, adding better
structured IP-core version interface, adding iATU regions size detection
and the PCIe regions verification procedure, adding dma-ranges support,
introducing a set of generic platform clocks and resets and finally adding
Baikal-T1 PCIe interface support will be submitted in the next part of the
series.

Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
Changelog v2:
- Fix the end address of the example in the patch log with
  the INCREASE_REGION_SIZE flag usage fixup. It should be
  0x1000FFFF and not 0x0000FFFF (@Manivannan).
- Add the cleanup-on-error path to the dw_pcie_ep_init() function.
  (@Manivannan)

Link: https://lore.kernel.org/linux-pci/20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru/
Changelog v3:
- Convert region variable type to u32 in order to fix the implicit type
  conversion peculiarity. (@kbot)
- Rebase onto v5.18-rc6.

Link: https://lore.kernel.org/linux-pci/20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru/
Changelog v4:
- Move the patch "PCI: dwc: Deallocate EPC memory on EP init error" to
  being applied before the cleanup patches.
- Add a new fixes patch: "PCI: dwc: Enable CDM-check independently from
  the num_lanes value".
- Add a new cleanup patch: "PCI: dwc: Organize local variables usage".
- Add a new cleanup patch: "PCI: dwc: Re-use local pointer to the
  resource data".
- Add a new cleanup patch: "PCI: dwc: Add start_link/stop_link inliners".
- Add a new cleanup patch: "PCI: dwc: Move io_cfg_atu_shared to the Root
  Port descriptor".
- Add a new cleanup patch: "PCI: dwc: Add dw_ prefix to the pcie_port
  structure name".
- Drop the patch "PCI: dwc: Don't use generic IO-ops for DBI-space
  access". (@Rob)
- Drop Manivannan tested tag from the changed patches.
- Rebase onto v5.18.

Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru/
Changelog v5:
- Just resend the series.
- Rebase onto v5.19-rcX.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: "Krzysztof Wilczyński" <kw@linux.com>
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-pci@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Serge Semin (18):
  PCI: dwc: Stop link in the host init error and de-initialization
  PCI: dwc: Add unroll iATU space support to the regions disable method
  PCI: dwc: Disable outbound windows for controllers with iATU
  PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
  PCI: dwc: Deallocate EPC memory on EP init error
  PCI: dwc: Enable CDM-check independently from the num_lanes value
  PCI: dwc: Add braces to the multi-line if-else statements
  PCI: dwc: Add trailing new-line literals to the log messages
  PCI: dwc: Discard IP-core version checking on unrolled iATU detection
  PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()
  PCI: dwc: Organize local variables usage
  PCI: dwc: Re-use local pointer to the resource data
  PCI: dwc: Add start_link/stop_link inliners
  PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor
  PCI: dwc: Add dw_ prefix to the pcie_port structure name
  PCI: dwc-plat: Simplify the probe method return value handling
  PCI: dwc-plat: Discard unused regmap pointer
  PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration

 drivers/pci/controller/dwc/pci-dra7xx.c       |  12 +--
 drivers/pci/controller/dwc/pci-exynos.c       |   6 +-
 drivers/pci/controller/dwc/pci-imx6.c         |   6 +-
 drivers/pci/controller/dwc/pci-keystone.c     |  20 ++--
 .../pci/controller/dwc/pci-layerscape-ep.c    |  12 ---
 drivers/pci/controller/dwc/pci-layerscape.c   |   2 +-
 drivers/pci/controller/dwc/pci-meson.c        |   2 +-
 drivers/pci/controller/dwc/pcie-al.c          |   6 +-
 drivers/pci/controller/dwc/pcie-armada8k.c    |   4 +-
 drivers/pci/controller/dwc/pcie-artpec6.c     |   4 +-
 .../pci/controller/dwc/pcie-designware-ep.c   |  30 ++++--
 .../pci/controller/dwc/pcie-designware-host.c | 102 ++++++++++--------
 .../pci/controller/dwc/pcie-designware-plat.c |  25 ++---
 drivers/pci/controller/dwc/pcie-designware.c  |  72 +++++++------
 drivers/pci/controller/dwc/pcie-designware.h  |  46 +++++---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c |   4 +-
 drivers/pci/controller/dwc/pcie-fu740.c       |   2 +-
 drivers/pci/controller/dwc/pcie-histb.c       |  10 +-
 drivers/pci/controller/dwc/pcie-intel-gw.c    |   6 +-
 drivers/pci/controller/dwc/pcie-keembay.c     |   4 +-
 drivers/pci/controller/dwc/pcie-kirin.c       |   2 +-
 drivers/pci/controller/dwc/pcie-qcom.c        |   4 +-
 drivers/pci/controller/dwc/pcie-spear13xx.c   |   6 +-
 drivers/pci/controller/dwc/pcie-tegra194.c    |  22 ++--
 drivers/pci/controller/dwc/pcie-uniphier.c    |  10 +-
 drivers/pci/controller/dwc/pcie-visconti.c    |   6 +-
 26 files changed, 224 insertions(+), 201 deletions(-)

-- 
2.35.1

[PATCH RESEND v5 01/18] PCI: dwc: Stop link in the host init error and de-initialization

[Serge Semin]

It's logically correct to undo everything what was done in case of an
error is discovered or in the corresponding cleanup counterpart. Otherwise
the host controller will be left in an undetermined state. Seeing the link
is set up in the Host-initialization method it will be right to
de-activate it there in the cleanup-on-error block and stop the link in
the antagonistic routine - dw_pcie_host_deinit(). The link de-activation
is a platform-specific thing and is supposed to be implemented in the
framework of the dw_pcie_ops.stop_link() operation.

Fixes: 886a9c134755 ("PCI: dwc: Move link handling into common code")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../pci/controller/dwc/pcie-designware-host.c    | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 9979302532b7..bc9a7df130ef 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -421,8 +421,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	bridge->sysdata = pp;
 
 	ret = pci_host_probe(bridge);
-	if (!ret)
-		return 0;
+	if (ret)
+		goto err_stop_link;
+
+	return 0;
+
+err_stop_link:
+	if (pci->ops && pci->ops->stop_link)
+		pci->ops->stop_link(pci);
 
 err_free_msi:
 	if (pp->has_msi_ctrl)
@@ -433,8 +439,14 @@ EXPORT_SYMBOL_GPL(dw_pcie_host_init);
 
 void dw_pcie_host_deinit(struct pcie_port *pp)
 {
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+
 	pci_stop_root_bus(pp->bridge->bus);
 	pci_remove_root_bus(pp->bridge->bus);
+
+	if (pci->ops && pci->ops->stop_link)
+		pci->ops->stop_link(pci);
+
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
 }
-- 
2.35.1

[PATCH RESEND v5 02/18] PCI: dwc: Add unroll iATU space support to the regions disable method

[Serge Semin]

The dw_pcie_disable_atu() method was introduced in the commit f8aed6ec624f
("PCI: dwc: designware: Add EP mode support"). Since then it hasn't
changed at all.  For all that time the method has supported the viewport
version of the iATU CSRs only. Basically it works for the DW PCIe IP-cores
older than v4.80a since the newer controllers are equipped with the
unrolled iATU/eDMA space. It means the methods using it like
pci_epc_ops.clear_bar and pci_epc_ops.unmap_addr callbacks just don't work
correctly for the DW PCIe controllers with unrolled iATU CSRs. The same
concerns the dw_pcie_setup_rc() method, which disables the outbound iATU
entries before re-initializing them.

So in order to fix the problems denoted above let's convert the
dw_pcie_disable_atu() method to disabling the iATU inbound and outbound
regions in the unrolled iATU CSRs in case the DW PCIe controller has been
synthesized with the ones support. The former semantics will be remained
for the controller having iATU mapped over the viewport.

Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v3:
- Convert region variable type to u32 in order to fix the implicit type
  conversion peculiarity. (@kbot)
---
 drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index d92c8a25094f..84fef21efdbc 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -491,7 +491,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
 			 enum dw_pcie_region_type type)
 {
-	int region;
+	u32 region;
 
 	switch (type) {
 	case DW_PCIE_REGION_INBOUND:
@@ -504,8 +504,18 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
 		return;
 	}
 
-	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
+	if (pci->iatu_unroll_enabled) {
+		if (region == PCIE_ATU_REGION_INBOUND) {
+			dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
+						 ~(u32)PCIE_ATU_ENABLE);
+		} else {
+			dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
+						 ~(u32)PCIE_ATU_ENABLE);
+		}
+	} else {
+		dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
+		dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
+	}
 }
 
 int dw_pcie_wait_for_link(struct dw_pcie *pci)
-- 
2.35.1

[PATCH RESEND v5 03/18] PCI: dwc: Disable outbound windows for controllers with iATU

[Serge Semin]

In accordance with the dw_pcie_setup_rc() method semantics and judging by
what the comment added in commit dd193929d91e ("PCI: designware: Explain
why we don't program ATU for some platforms") states there are DWC
PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's
Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU
enabled and use it's own address translation approach implemented. In
these cases at the very least there is no point in touching the DW PCIe
iATU CSRs. Moreover depending on the vendor-specific address translation
implementation it might be even erroneous. So let's move the iATU windows
disabling procedure to being under the corresponding conditional statement
clause thus performing that procedure only if the iATU is expected to be
available on the platform.

Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index bc9a7df130ef..d4326aae5a32 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -543,7 +543,6 @@ static struct pci_ops dw_pcie_ops = {
 
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
-	int i;
 	u32 val, ctrl, num_ctrls;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
@@ -594,19 +593,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 		PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
 	dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 
-	/* Ensure all outbound windows are disabled so there are multiple matches */
-	for (i = 0; i < pci->num_ob_windows; i++)
-		dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
-
 	/*
 	 * If the platform provides its own child bus config accesses, it means
 	 * the platform uses its own address translation component rather than
 	 * ATU, so we should not program the ATU here.
 	 */
 	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
-		int atu_idx = 0;
+		int i, atu_idx = 0;
 		struct resource_entry *entry;
 
+		/*
+		 * Ensure all outbound windows are disabled so there are
+		 * multiple matches
+		 */
+		for (i = 0; i < pci->num_ob_windows; i++)
+			dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
+
 		/* Get last memory resource entry */
 		resource_list_for_each_entry(entry, &pp->bridge->windows) {
 			if (resource_type(entry->res) != IORESOURCE_MEM)
-- 
2.35.1

[PATCH RESEND v5 04/18] PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address

[Serge Semin]

It was wrong to use the region size parameter in order to determine
whether the INCREASE_REGION_SIZE flag needs to be set for the outbound
iATU entry because in general there are cases when combining a region base
address and size together produces the out of bounds upper range limit
while upper_32_bits(size) still returns zero. So having a region size
within the permitted values doesn't mean the region limit address will fit
to the corresponding CSR. Here is the way iATU calculates the in- and
outbound untranslated regions if the INCREASE_REGION_SIZE flag is cleared
[1]:

  Start address:                      End address:
63              31              0   63              31              0
+---------------+---------------+   +---------------+---------------+
|               |         |  0s |   |               |         |  Fs |
+---------------+---------------+   +---------------+---------------+
   upper base   |   lower base       !upper! base   | limit address
     address          address           address

So the region start address is determined by the iATU lower and upper base
address registers, while the region upper boundary is calculated based on
the 32-bits limit address register and the upper part of the base address.
In accordance with that logic for instance the range
0xf0000000 @ 0x20000000 does have the size smaller than 4GB, but the
actual limit address turns to be invalid forming the untranslated address
map as [0xf0000000; 0x1000FFFF], which isn't what the original range was.
In order to fix that we need to check whether the size after being added
to the lower part of the base address causes the 4GB range overflow. If it
does then we need to set the INCREASE_REGION_SIZE flag thus activating the
extended limit address by means of an additional iATU CSR (upper limit
address register) [2]:

  Start address:                      End address:
63              31              0   63      x       31              0
+---------------+---------------+   +---------------+---------------+
|               |         |  0s |   |       |       |         |  Fs |
+---------------+---------------+   +---------------+---------------+
   upper base   |  lower base         upper | upper | limit address
     address         address          base  | limit |
                                     address|address|

Otherwise there is enough room in the 32-bits wide limit address register,
and the flag can be left unset.

Note the case when the size-based flag setting approach is correct implies
requiring to have the size-aligned base addresses only. But that
constraint isn't relevant to the PCIe ranges accepted by the kernel.
There is also no point in implementing it either seeing the problem can be
easily fixed by checking the whole limit address instead of the region
size.

[1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    v5.40a, March 2019, fig.3-36, p.175
[2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
    v5.40a, March 2019, fig.3-37, p.176

Fixes: 5b4cf0f65324 ("PCI: dwc: Add upper limit address for outbound iATU")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v2:
- Fix the end address in the example of the patch log. It should be
  0x1000FFFF and not 0x0000FFFF (@Manivannan).
---
 drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 84fef21efdbc..347251bf87d0 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -287,8 +287,8 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
 				 upper_32_bits(pci_addr));
 	val = type | PCIE_ATU_FUNC_NUM(func_no);
-	val = upper_32_bits(size - 1) ?
-		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
+	if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr))
+		val |= PCIE_ATU_INCREASE_REGION_SIZE;
 	if (pci->version == 0x490A)
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
@@ -315,6 +315,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
 					u64 pci_addr, u64 size)
 {
 	u32 retries, val;
+	u64 limit_addr;
 
 	if (pci->ops && pci->ops->cpu_addr_fixup)
 		cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
@@ -325,6 +326,8 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
 		return;
 	}
 
+	limit_addr = cpu_addr + size - 1;
+
 	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
 			   PCIE_ATU_REGION_OUTBOUND | index);
 	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
@@ -332,17 +335,18 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
 	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
 			   upper_32_bits(cpu_addr));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
-			   lower_32_bits(cpu_addr + size - 1));
+			   lower_32_bits(limit_addr));
 	if (pci->version >= 0x460A)
 		dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
-				   upper_32_bits(cpu_addr + size - 1));
+				   upper_32_bits(limit_addr));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
 			   lower_32_bits(pci_addr));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
 			   upper_32_bits(pci_addr));
 	val = type | PCIE_ATU_FUNC_NUM(func_no);
-	val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ?
-		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
+	if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
+	    pci->version >= 0x460A)
+		val |= PCIE_ATU_INCREASE_REGION_SIZE;
 	if (pci->version == 0x490A)
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
-- 
2.35.1

[PATCH RESEND v5 05/18] PCI: dwc: Deallocate EPC memory on EP init error

[Serge Semin]

If the dw_pcie_ep_init() method fails to perform any action after the EPC
memory is initialized and the MSI memory region is allocated, the later
parts won't be undone thus causing the memory leak.  Let's fix that by
introducing the cleanup-on-error path in the dw_pcie_ep_init() method,
which will be taken should any consequent erroneous situation happens.

Fixes: 2fd0c9d966cc ("PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v2:
- This is a new patch create as a result of the discussion in:
  Link: https://lore.kernel.org/linux-pci/20220324014836.19149-26-Sergey.Semin@baikalelectronics.ru
---
 .../pci/controller/dwc/pcie-designware-ep.c    | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 0eda8236c125..13c2e73f0eaf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -780,8 +780,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
 					     epc->mem->window.page_size);
 	if (!ep->msi_mem) {
+		ret = -ENOMEM;
 		dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
-		return -ENOMEM;
+		goto err_exit_epc_mem;
 	}
 
 	if (ep->ops->get_features) {
@@ -790,6 +791,19 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 			return 0;
 	}
 
-	return dw_pcie_ep_init_complete(ep);
+	ret = dw_pcie_ep_init_complete(ep);
+	if (ret)
+		goto err_free_epc_mem;
+
+	return 0;
+
+err_free_epc_mem:
+	pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
+			      epc->mem->window.page_size);
+
+err_exit_epc_mem:
+	pci_epc_mem_exit(epc);
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(dw_pcie_ep_init);
-- 
2.35.1

[PATCH RESEND v5 06/18] PCI: dwc: Enable CDM-check independently from the num_lanes value

[Serge Semin]

Currently the embedded CDM IOs consistency check-engine is enabled only if
the num_lanes field of dw_pcie structure is set to non-zero value. It's
definitely wrong since the CDM checking has nothing to do with the PCIe
lanes settings, while that feature will be left disabled for the platforms
which expect it being enabled and prefer keeping the default lanes setup.
Let's fix that by enabling the CDM-check feature before the num_lanes
parameter is handled.

Fixes: 07f123def73e ("PCI: dwc: Add support to enable CDM register check")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v4:
- This is a new patch created on v4 lap of the series.
---
 drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 347251bf87d0..5848cc520b52 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -740,6 +740,13 @@ void dw_pcie_setup(struct dw_pcie *pci)
 	val |= PORT_LINK_DLL_LINK_EN;
 	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 
+	if (of_property_read_bool(np, "snps,enable-cdm-check")) {
+		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
+		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
+		       PCIE_PL_CHK_REG_CHK_REG_START;
+		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
+	}
+
 	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
 	if (!pci->num_lanes) {
 		dev_dbg(pci->dev, "Using h/w default number of lanes\n");
@@ -786,11 +793,4 @@ void dw_pcie_setup(struct dw_pcie *pci)
 		break;
 	}
 	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
-
-	if (of_property_read_bool(np, "snps,enable-cdm-check")) {
-		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
-		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
-		       PCIE_PL_CHK_REG_CHK_REG_START;
-		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
-	}
 }
-- 
2.35.1

[PATCH RESEND v5 07/18] PCI: dwc: Add braces to the multi-line if-else statements

[Serge Semin]

In accordance with [1] if there is at least one multi-line if-else
clause in the statement, then each clause will need to be surrounded by
the braces. The driver code violates that coding style rule in a few
places. Let's fix it.

[1] Documentation/process/coding-style.rst

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++--
 drivers/pci/controller/dwc/pcie-designware.c    | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 13c2e73f0eaf..7ad349c32082 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -699,9 +699,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 
 	if (!pci->dbi_base2) {
 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
-		if (!res)
+		if (!res) {
 			pci->dbi_base2 = pci->dbi_base + SZ_4K;
-		else {
+		} else {
 			pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res);
 			if (IS_ERR(pci->dbi_base2))
 				return PTR_ERR(pci->dbi_base2);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 5848cc520b52..d0061735b434 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -699,8 +699,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 			pci->atu_size = SZ_4K;
 
 		dw_pcie_iatu_detect_regions_unroll(pci);
-	} else
+	} else {
 		dw_pcie_iatu_detect_regions(pci);
+	}
 
 	dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
 		"enabled" : "disabled");
-- 
2.35.1

[PATCH RESEND v5 08/18] PCI: dwc: Add trailing new-line literals to the log messages

[Serge Semin]

There are two places in the DW PCIe controller driver, which omit the
trailing newlines in the log info and warn messages. Not having them there
will cause leaving the messages in the printk ring buffer until a next
'\n'-terminated message is printed (it will consequently cause the buffer
flush). As it isn't what the corresponding code implies let's add the
new-line characters in the messages.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-
 drivers/pci/controller/dwc/pcie-designware.c      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d4326aae5a32..9a4922b714e5 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -633,7 +633,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 		}
 
 		if (pci->num_ob_windows <= atu_idx)
-			dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
+			dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
 				 pci->num_ob_windows);
 	}
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index d0061735b434..ac966ed28c5b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -706,7 +706,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 	dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
 		"enabled" : "disabled");
 
-	dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound",
+	dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound\n",
 		 pci->num_ob_windows, pci->num_ib_windows);
 }
 
-- 
2.35.1

[PATCH RESEND v5 09/18] PCI: dwc: Discard IP-core version checking on unrolled iATU detection

[Serge Semin]

It's pretty much pointless. Even though unrolled version of the internal
ATU has been indeed available since DWC PCIe v4.80a IP-core, there is no
guarantee it was enabled during the IP-core configuration (Synopsys
suggests to contact the Solvnet support for guidance of how to do that for
the newer IP-cores). So the only reliable way to find out the unrolled
iATU feature availability is indeed to check the iATU viewport register
content. In accordance with the reference manual [1] if the register
doesn't exist (unrolled iATU is enabled) it's content is fixed with
0xff-s, otherwise it will contain some zeros. So we can freely drop the
IP-core version checking in this matter then and use the
dw_pcie_iatu_unroll_enabled() method only to detect whether iATU/eDMA
space is unrolled.

[1] DesignWare Cores, PCI Express Controller, Register Desciptions,
v.4.90a, December 2016, p.855

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index ac966ed28c5b..e5c30695f664 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -600,15 +600,15 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
 
 }
 
-static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
+static bool dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
 {
 	u32 val;
 
 	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
 	if (val == 0xffffffff)
-		return 1;
+		return true;
 
-	return 0;
+	return false;
 }
 
 static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci)
@@ -680,9 +680,8 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 	struct device *dev = pci->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 
-	if (pci->version >= 0x480A || (!pci->version &&
-				       dw_pcie_iatu_unroll_enabled(pci))) {
-		pci->iatu_unroll_enabled = true;
+	pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
+	if (pci->iatu_unroll_enabled) {
 		if (!pci->atu_base) {
 			struct resource *res =
 				platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
-- 
2.35.1

[PATCH RESEND v5 10/18] PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()

[Serge Semin]

While the rest of the generic DWC PCIe code is using the dedicated IO-mem
accessors, the dw_pcie_link_up() method for some unobvious reason directly
calls readl() to get PortLogic.DEBUG1 register content. Since the way the
dbi-bus is accessed can be platform-specific let's replace the direct dbi
memory space read procedure with the readl-wrapper invocation. Thus we'll
have a slightly more generic dw_pcie_link_up() method.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index e5c30695f664..f9613835212b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -548,7 +548,7 @@ int dw_pcie_link_up(struct dw_pcie *pci)
 	if (pci->ops && pci->ops->link_up)
 		return pci->ops->link_up(pci);
 
-	val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
 	return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
 		(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
 }
-- 
2.35.1

[PATCH RESEND v5 11/18] PCI: dwc: Organize local variables usage

[Serge Semin]

There are several places in the common DW PCIe code with incoherent local
variables usage: a variable is defined and initialized with a structure
field, but the structure pointer is de-referenced to access that field
anyway; the local variable is defined and initialized but either used just
once or not used afterwards in the main part of the subsequent method.
It's mainly concerns the pcie_port.dev field. Let's fix that in the
relevant places.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------
 drivers/pci/controller/dwc/pcie-designware.c      |  8 +++-----
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 9a4922b714e5..54257874c154 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -296,7 +296,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	struct resource *cfg_res;
 	int ret;
 
-	raw_spin_lock_init(&pci->pp.lock);
+	raw_spin_lock_init(&pp->lock);
 
 	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
 	if (cfg_res) {
@@ -388,15 +388,15 @@ int dw_pcie_host_init(struct pcie_port *pp)
 							    dw_chained_msi_isr,
 							    pp);
 
-			ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
+			ret = dma_set_mask(dev, DMA_BIT_MASK(32));
 			if (ret)
-				dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
+				dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
 
-			pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
+			pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
 						      sizeof(pp->msi_msg),
 						      DMA_FROM_DEVICE,
 						      DMA_ATTR_SKIP_CPU_SYNC);
-			ret = dma_mapping_error(pci->dev, pp->msi_data);
+			ret = dma_mapping_error(dev, pp->msi_data);
 			if (ret) {
 				dev_err(pci->dev, "Failed to map MSI data\n");
 				pp->msi_data = 0;
@@ -633,7 +633,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 		}
 
 		if (pci->num_ob_windows <= atu_idx)
-			dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
+			dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",
 				 pci->num_ob_windows);
 	}
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index f9613835212b..ce01187947c9 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -677,8 +677,7 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
 
 void dw_pcie_iatu_detect(struct dw_pcie *pci)
 {
-	struct device *dev = pci->dev;
-	struct platform_device *pdev = to_platform_device(dev);
+	struct platform_device *pdev = to_platform_device(pci->dev);
 
 	pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
 	if (pci->iatu_unroll_enabled) {
@@ -687,7 +686,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 				platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
 			if (res) {
 				pci->atu_size = resource_size(res);
-				pci->atu_base = devm_ioremap_resource(dev, res);
+				pci->atu_base = devm_ioremap_resource(pci->dev, res);
 			}
 			if (!pci->atu_base || IS_ERR(pci->atu_base))
 				pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
@@ -711,9 +710,8 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 
 void dw_pcie_setup(struct dw_pcie *pci)
 {
+	struct device_node *np = pci->dev->of_node;
 	u32 val;
-	struct device *dev = pci->dev;
-	struct device_node *np = dev->of_node;
 
 	if (pci->link_gen > 0)
 		dw_pcie_link_set_max_speed(pci, pci->link_gen);
-- 
2.35.1

[PATCH RESEND v5 12/18] PCI: dwc: Re-use local pointer to the resource data

[Serge Semin]

The dw_pcie_host_init() method has two instances of the resource structure
pointers used in non-related places of the method. It's pointless to have
two different local storages for them since the corresponding code is
small and having resource specific names doesn't make it more readable.
Let's convert these parts of the function to using just a common pointer
to the resource structure instance. That shall make the code a bit nicer
looking.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
 .../pci/controller/dwc/pcie-designware-host.c    | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 54257874c154..2f13eec4812d 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -293,17 +293,17 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct resource_entry *win;
 	struct pci_host_bridge *bridge;
-	struct resource *cfg_res;
+	struct resource *res;
 	int ret;
 
 	raw_spin_lock_init(&pp->lock);
 
-	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
-	if (cfg_res) {
-		pp->cfg0_size = resource_size(cfg_res);
-		pp->cfg0_base = cfg_res->start;
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+	if (res) {
+		pp->cfg0_size = resource_size(res);
+		pp->cfg0_base = res->start;
 
-		pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res);
+		pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
 		if (IS_ERR(pp->va_cfg0_base))
 			return PTR_ERR(pp->va_cfg0_base);
 	} else {
@@ -312,8 +312,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	}
 
 	if (!pci->dbi_base) {
-		struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
-		pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+		pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
 		if (IS_ERR(pci->dbi_base))
 			return PTR_ERR(pci->dbi_base);
 	}
-- 
2.35.1

[PATCH RESEND v5 13/18] PCI: dwc: Add start_link/stop_link inliners

[Serge Semin]

There are several places in the generic DW PCIe code where the
platform-specific PCIe link start/stop methods are called after making
sure the ops handler and the callbacks are specified. Instead of repeating
the same pattern over and over let's define the static-inline methods in
the DW PCIe header file and use them in the relevant parts of the driver.

Note returning a negative error from the EP link start procedure if the
start_link pointer isn't specified doesn't really make much sense since
it's perfectly normal to have such a platform. Moreover even
pci_epc_start() doesn't fail if no epc->ops->start callback is spotted. As
a side-effect of this modification we can set the generic DW PCIe and
Layerscape EP platform drivers free from the empty start_link callbacks
and as such entirely dummy dw_pcie_ops instances.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
 drivers/pci/controller/dwc/pci-layerscape-ep.c    | 12 ------------
 drivers/pci/controller/dwc/pcie-designware-ep.c   |  8 ++------
 drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++------
 drivers/pci/controller/dwc/pcie-designware-plat.c | 10 ----------
 drivers/pci/controller/dwc/pcie-designware.h      | 14 ++++++++++++++
 5 files changed, 20 insertions(+), 34 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 39f4664bd84c..ad99707b3b99 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -32,15 +32,6 @@ struct ls_pcie_ep {
 	const struct ls_pcie_ep_drvdata *drvdata;
 };
 
-static int ls_pcie_establish_link(struct dw_pcie *pci)
-{
-	return 0;
-}
-
-static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
-	.start_link = ls_pcie_establish_link,
-};
-
 static const struct pci_epc_features*
 ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
 {
@@ -106,19 +97,16 @@ static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
 
 static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
 	.ops = &ls_pcie_ep_ops,
-	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
 };
 
 static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
 	.func_offset = 0x20000,
 	.ops = &ls_pcie_ep_ops,
-	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
 };
 
 static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = {
 	.func_offset = 0x8000,
 	.ops = &ls_pcie_ep_ops,
-	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
 };
 
 static const struct of_device_id ls_pcie_ep_of_match[] = {
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7ad349c32082..15b8059544e3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -435,8 +435,7 @@ static void dw_pcie_ep_stop(struct pci_epc *epc)
 	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-	if (pci->ops && pci->ops->stop_link)
-		pci->ops->stop_link(pci);
+	dw_pcie_stop_link(pci);
 }
 
 static int dw_pcie_ep_start(struct pci_epc *epc)
@@ -444,10 +443,7 @@ static int dw_pcie_ep_start(struct pci_epc *epc)
 	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-	if (!pci->ops || !pci->ops->start_link)
-		return -EINVAL;
-
-	return pci->ops->start_link(pci);
+	return dw_pcie_start_link(pci);
 }
 
 static const struct pci_epc_features*
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 2f13eec4812d..c49a3bde7a2a 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -409,8 +409,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 
 	dw_pcie_setup_rc(pp);
 
-	if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
-		ret = pci->ops->start_link(pci);
+	if (!dw_pcie_link_up(pci)) {
+		ret = dw_pcie_start_link(pci);
 		if (ret)
 			goto err_free_msi;
 	}
@@ -427,8 +427,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	return 0;
 
 err_stop_link:
-	if (pci->ops && pci->ops->stop_link)
-		pci->ops->stop_link(pci);
+	dw_pcie_stop_link(pci);
 
 err_free_msi:
 	if (pp->has_msi_ctrl)
@@ -444,8 +443,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp)
 	pci_stop_root_bus(pp->bridge->bus);
 	pci_remove_root_bus(pp->bridge->bus);
 
-	if (pci->ops && pci->ops->stop_link)
-		pci->ops->stop_link(pci);
+	dw_pcie_stop_link(pci);
 
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 0c5de87d3cc6..abf1afac6064 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -36,15 +36,6 @@ static const struct of_device_id dw_plat_pcie_of_match[];
 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
 };
 
-static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
-{
-	return 0;
-}
-
-static const struct dw_pcie_ops dw_pcie_ops = {
-	.start_link = dw_plat_pcie_establish_link,
-};
-
 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -140,7 +131,6 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	pci->dev = dev;
-	pci->ops = &dw_pcie_ops;
 
 	dw_plat_pcie->pci = pci;
 	dw_plat_pcie->mode = mode;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 7d6e9b7576be..8ba239292634 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -365,6 +365,20 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
 	dw_pcie_writel_dbi(pci, reg, val);
 }
 
+static inline int dw_pcie_start_link(struct dw_pcie *pci)
+{
+	if (pci->ops && pci->ops->start_link)
+		return pci->ops->start_link(pci);
+
+	return 0;
+}
+
+static inline void dw_pcie_stop_link(struct dw_pcie *pci)
+{
+	if (pci->ops && pci->ops->stop_link)
+		pci->ops->stop_link(pci);
+}
+
 #ifdef CONFIG_PCIE_DW_HOST
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
-- 
2.35.1

[PATCH RESEND v5 14/18] PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor

[Serge Semin]

That flag is set if there is an outbound iATU window used for both PCIe
peripheral config-space accesses and IO ports transfers. Since the flag
semantic is purely Root Port specific, it's unused in neither the DW PCIe
common code nor in the DW PCIe Endpoint driver, we can freely move it to
the DW PCIe Root Port descriptor. Thus the pcie_port structure will be
more coherent.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++---
 drivers/pci/controller/dwc/pcie-designware.h      | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index c49a3bde7a2a..7ff2b7555b91 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -492,7 +492,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
 
 	ret = pci_generic_config_read(bus, devfn, where, size, val);
 
-	if (!ret && pci->io_cfg_atu_shared)
+	if (!ret && pp->cfg0_io_shared)
 		dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
 					  pp->io_bus_addr, pp->io_size);
 
@@ -508,7 +508,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
 
 	ret = pci_generic_config_write(bus, devfn, where, size, val);
 
-	if (!ret && pci->io_cfg_atu_shared)
+	if (!ret && pp->cfg0_io_shared)
 		dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
 					  pp->io_bus_addr, pp->io_size);
 
@@ -627,7 +627,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 							  PCIE_ATU_TYPE_IO, pp->io_base,
 							  pp->io_bus_addr, pp->io_size);
 			else
-				pci->io_cfg_atu_shared = true;
+				pp->cfg0_io_shared = true;
 		}
 
 		if (pci->num_ob_windows <= atu_idx)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 8ba239292634..13bffa3eaed6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -179,6 +179,7 @@ struct dw_pcie_host_ops {
 
 struct pcie_port {
 	bool			has_msi_ctrl:1;
+	bool			cfg0_io_shared:1;
 	u64			cfg0_base;
 	void __iomem		*va_cfg0_base;
 	u32			cfg0_size;
@@ -274,7 +275,6 @@ struct dw_pcie {
 	int			link_gen;
 	u8			n_fts[2];
 	bool			iatu_unroll_enabled: 1;
-	bool			io_cfg_atu_shared: 1;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
-- 
2.35.1

[PATCH RESEND v5 15/18] PCI: dwc: Add dw_ prefix to the pcie_port structure name

[Serge Semin]

All of the DW PCIe core driver entities have names with the dw_ prefix in
order to easily distinguish local and common PCIe name spaces. All except
the pcie_port structure which contains the DW PCIe Root Port descriptor.
For historical reason the structure has retained the original name since
commit 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos") when
the DW PCIe IP-core support was added to the kernel. Let's finally fix
that by adding the dw_ prefix to the structure name and by adding the _rp
suffix to be similar to the EP counterpart. Thus the name will be coherent
with the common driver naming policy. It shall make the driver code more
readable eliminating visual confusion between the local and generic PCI
name spaces.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>

---

Changelog v4:
- This is a new patch created on the v4 lap of the series.
---
 drivers/pci/controller/dwc/pci-dra7xx.c       | 12 +++----
 drivers/pci/controller/dwc/pci-exynos.c       |  6 ++--
 drivers/pci/controller/dwc/pci-imx6.c         |  6 ++--
 drivers/pci/controller/dwc/pci-keystone.c     | 20 +++++------
 drivers/pci/controller/dwc/pci-layerscape.c   |  2 +-
 drivers/pci/controller/dwc/pci-meson.c        |  2 +-
 drivers/pci/controller/dwc/pcie-al.c          |  6 ++--
 drivers/pci/controller/dwc/pcie-armada8k.c    |  4 +--
 drivers/pci/controller/dwc/pcie-artpec6.c     |  4 +--
 .../pci/controller/dwc/pcie-designware-host.c | 36 +++++++++----------
 .../pci/controller/dwc/pcie-designware-plat.c |  2 +-
 drivers/pci/controller/dwc/pcie-designware.h  | 30 ++++++++--------
 drivers/pci/controller/dwc/pcie-dw-rockchip.c |  4 +--
 drivers/pci/controller/dwc/pcie-fu740.c       |  2 +-
 drivers/pci/controller/dwc/pcie-histb.c       | 10 +++---
 drivers/pci/controller/dwc/pcie-intel-gw.c    |  6 ++--
 drivers/pci/controller/dwc/pcie-keembay.c     |  4 +--
 drivers/pci/controller/dwc/pcie-kirin.c       |  2 +-
 drivers/pci/controller/dwc/pcie-qcom.c        |  4 +--
 drivers/pci/controller/dwc/pcie-spear13xx.c   |  6 ++--
 drivers/pci/controller/dwc/pcie-tegra194.c    | 22 ++++++------
 drivers/pci/controller/dwc/pcie-uniphier.c    | 10 +++---
 drivers/pci/controller/dwc/pcie-visconti.c    |  6 ++--
 23 files changed, 103 insertions(+), 103 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index dfcdeb432dc8..a174b680b2a7 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -178,7 +178,7 @@ static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
 	dra7xx_pcie_enable_msi_interrupts(dra7xx);
 }
 
-static int dra7xx_pcie_host_init(struct pcie_port *pp)
+static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
@@ -202,7 +202,7 @@ static const struct irq_domain_ops intx_domain_ops = {
 	.xlate = pci_irqd_intx_xlate,
 };
 
-static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
+static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	unsigned long val;
@@ -224,7 +224,7 @@ static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
 	return 1;
 }
 
-static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
+static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	int ret, i, count, num_ctrls;
@@ -255,8 +255,8 @@ static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	struct dra7xx_pcie *dra7xx;
+	struct dw_pcie_rp *pp;
 	struct dw_pcie *pci;
-	struct pcie_port *pp;
 	unsigned long reg;
 	u32 bit;
 
@@ -344,7 +344,7 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
+static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct device *dev = pci->dev;
@@ -475,7 +475,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
 {
 	int ret;
 	struct dw_pcie *pci = dra7xx->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = pci->dev;
 
 	pp->irq = platform_get_irq(pdev, 1);
diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
index 467c8d1cd7e4..2044d191fba6 100644
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -249,7 +249,7 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
 	return (val & PCIE_ELBI_XMLH_LINKUP);
 }
 
-static int exynos_pcie_host_init(struct pcie_port *pp)
+static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct exynos_pcie *ep = to_exynos_pcie(pci);
@@ -276,7 +276,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep,
 				       struct platform_device *pdev)
 {
 	struct dw_pcie *pci = &ep->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = &pdev->dev;
 	int ret;
 
@@ -406,7 +406,7 @@ static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
 {
 	struct exynos_pcie *ep = dev_get_drvdata(dev);
 	struct dw_pcie *pci = &ep->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	int ret;
 
 	ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 7a285fb0f619..5ea01ed4674d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -863,7 +863,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
 	return ret;
 }
 
-static int imx6_pcie_host_init(struct pcie_port *pp)
+static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
@@ -992,7 +992,7 @@ static int imx6_pcie_resume_noirq(struct device *dev)
 {
 	int ret;
 	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
-	struct pcie_port *pp = &imx6_pcie->pci->pp;
+	struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
 
 	if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
 		return 0;
@@ -1291,7 +1291,7 @@ static struct platform_driver imx6_pcie_driver = {
 static void imx6_pcie_quirk(struct pci_dev *dev)
 {
 	struct pci_bus *bus = dev->bus;
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 
 	/* Bus parent is the PCI bridge, its parent is this platform driver */
 	if (!bus->dev.parent || !bus->dev.parent->parent)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index d10e5fd0f83c..c3d88aa27dd4 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -147,7 +147,7 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
 
 static void ks_pcie_msi_irq_ack(struct irq_data *data)
 {
-	struct pcie_port *pp  = irq_data_get_irq_chip_data(data);
+	struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(data);
 	struct keystone_pcie *ks_pcie;
 	u32 irq = data->hwirq;
 	struct dw_pcie *pci;
@@ -167,7 +167,7 @@ static void ks_pcie_msi_irq_ack(struct irq_data *data)
 
 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
 	struct keystone_pcie *ks_pcie;
 	struct dw_pcie *pci;
 	u64 msi_target;
@@ -192,7 +192,7 @@ static int ks_pcie_msi_set_affinity(struct irq_data *irq_data,
 
 static void ks_pcie_msi_mask(struct irq_data *data)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
 	struct keystone_pcie *ks_pcie;
 	u32 irq = data->hwirq;
 	struct dw_pcie *pci;
@@ -216,7 +216,7 @@ static void ks_pcie_msi_mask(struct irq_data *data)
 
 static void ks_pcie_msi_unmask(struct irq_data *data)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
 	struct keystone_pcie *ks_pcie;
 	u32 irq = data->hwirq;
 	struct dw_pcie *pci;
@@ -247,7 +247,7 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
 	.irq_unmask = ks_pcie_msi_unmask,
 };
 
-static int ks_pcie_msi_host_init(struct pcie_port *pp)
+static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
 {
 	pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
 	return dw_pcie_allocate_domains(pp);
@@ -390,7 +390,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
 	u32 val;
 	u32 num_viewport = ks_pcie->num_viewport;
 	struct dw_pcie *pci = ks_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	u64 start, end;
 	struct resource *mem;
 	int i;
@@ -428,7 +428,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
 					   unsigned int devfn, int where)
 {
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 	u32 reg;
@@ -456,7 +456,7 @@ static struct pci_ops ks_child_pcie_ops = {
  */
 static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
 {
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 
@@ -574,7 +574,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
 	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 	u32 offset = irq - ks_pcie->msi_host_irq;
 	struct dw_pcie *pci = ks_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = pci->dev;
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	u32 vector, reg, pos;
@@ -799,7 +799,7 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
 	return 0;
 }
 
-static int __init ks_pcie_host_init(struct pcie_port *pp)
+static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index 6a4f0619bb1c..879b8692f96a 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -74,7 +74,7 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
 	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
 }
 
-static int ls_pcie_host_init(struct pcie_port *pp)
+static int ls_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct ls_pcie *pcie = to_ls_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index f44bf347904a..c1527693bed9 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -370,7 +370,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci)
 	return 0;
 }
 
-static int meson_pcie_host_init(struct pcie_port *pp)
+static int meson_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct meson_pcie *mp = to_meson_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c
index e8afa50129a8..b8cb77c9c4bd 100644
--- a/drivers/pci/controller/dwc/pcie-al.c
+++ b/drivers/pci/controller/dwc/pcie-al.c
@@ -217,7 +217,7 @@ static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
 static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus,
 					       unsigned int devfn, int where)
 {
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
 	unsigned int busnr = bus->number;
 	struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
@@ -245,7 +245,7 @@ static struct pci_ops al_child_pci_ops = {
 static void al_pcie_config_prepare(struct al_pcie *pcie)
 {
 	struct al_pcie_target_bus_cfg *target_bus_cfg;
-	struct pcie_port *pp = &pcie->pci->pp;
+	struct dw_pcie_rp *pp = &pcie->pci->pp;
 	unsigned int ecam_bus_mask;
 	u32 cfg_control_offset;
 	u8 subordinate_bus;
@@ -289,7 +289,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie)
 	al_pcie_controller_writel(pcie, cfg_control_offset, reg);
 }
 
-static int al_pcie_host_init(struct pcie_port *pp)
+static int al_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct al_pcie *pcie = to_al_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index 4e2552dcf982..8b113d3f3095 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -166,7 +166,7 @@ static int armada8k_pcie_start_link(struct dw_pcie *pci)
 	return 0;
 }
 
-static int armada8k_pcie_host_init(struct pcie_port *pp)
+static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	u32 reg;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -233,7 +233,7 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
 				  struct platform_device *pdev)
 {
 	struct dw_pcie *pci = pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = &pdev->dev;
 	int ret;
 
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index 2f15441770e1..98102079e26d 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -97,7 +97,7 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
 static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
 {
 	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct dw_pcie_ep *ep = &pci->ep;
 
 	switch (artpec6_pcie->mode) {
@@ -315,7 +315,7 @@ static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
 	usleep_range(100, 200);
 }
 
-static int artpec6_pcie_host_init(struct pcie_port *pp)
+static int artpec6_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 7ff2b7555b91..95256434913f 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -53,7 +53,7 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
 };
 
 /* MSI int handler */
-irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
+irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
 {
 	int i, pos;
 	unsigned long val;
@@ -88,7 +88,7 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 static void dw_chained_msi_isr(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 
 	chained_irq_enter(chip, desc);
 
@@ -100,7 +100,7 @@ static void dw_chained_msi_isr(struct irq_desc *desc)
 
 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	u64 msi_target;
 
@@ -123,7 +123,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d,
 
 static void dw_pci_bottom_mask(struct irq_data *d)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	unsigned int res, bit, ctrl;
 	unsigned long flags;
@@ -142,7 +142,7 @@ static void dw_pci_bottom_mask(struct irq_data *d)
 
 static void dw_pci_bottom_unmask(struct irq_data *d)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	unsigned int res, bit, ctrl;
 	unsigned long flags;
@@ -161,7 +161,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d)
 
 static void dw_pci_bottom_ack(struct irq_data *d)
 {
-	struct pcie_port *pp  = irq_data_get_irq_chip_data(d);
+	struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(d);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	unsigned int res, bit, ctrl;
 
@@ -185,7 +185,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
 				    unsigned int virq, unsigned int nr_irqs,
 				    void *args)
 {
-	struct pcie_port *pp = domain->host_data;
+	struct dw_pcie_rp *pp = domain->host_data;
 	unsigned long flags;
 	u32 i;
 	int bit;
@@ -213,7 +213,7 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain,
 				    unsigned int virq, unsigned int nr_irqs)
 {
 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
-	struct pcie_port *pp = domain->host_data;
+	struct dw_pcie_rp *pp = domain->host_data;
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&pp->lock, flags);
@@ -229,7 +229,7 @@ static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
 	.free	= dw_pcie_irq_domain_free,
 };
 
-int dw_pcie_allocate_domains(struct pcie_port *pp)
+int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
@@ -255,7 +255,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
 	return 0;
 }
 
-static void dw_pcie_free_msi(struct pcie_port *pp)
+static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
 {
 	if (pp->msi_irq)
 		irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
@@ -272,7 +272,7 @@ static void dw_pcie_free_msi(struct pcie_port *pp)
 	}
 }
 
-static void dw_pcie_msi_init(struct pcie_port *pp)
+static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	u64 msi_target = (u64)pp->msi_data;
@@ -285,7 +285,7 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
 	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
 }
 
-int dw_pcie_host_init(struct pcie_port *pp)
+int dw_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct device *dev = pci->dev;
@@ -436,7 +436,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
 
-void dw_pcie_host_deinit(struct pcie_port *pp)
+void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
@@ -455,7 +455,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
 {
 	int type;
 	u32 busdev;
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
 	/*
@@ -487,7 +487,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
 				 int where, int size, u32 *val)
 {
 	int ret;
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
 	ret = pci_generic_config_read(bus, devfn, where, size, val);
@@ -503,7 +503,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
 				 int where, int size, u32 val)
 {
 	int ret;
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
 	ret = pci_generic_config_write(bus, devfn, where, size, val);
@@ -523,7 +523,7 @@ static struct pci_ops dw_child_pcie_ops = {
 
 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
 {
-	struct pcie_port *pp = bus->sysdata;
+	struct dw_pcie_rp *pp = bus->sysdata;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
 	if (PCI_SLOT(devfn) > 0)
@@ -539,7 +539,7 @@ static struct pci_ops dw_pcie_ops = {
 	.write = pci_generic_config_write,
 };
 
-void dw_pcie_setup_rc(struct pcie_port *pp)
+void dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 {
 	u32 val, ctrl, num_ctrls;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index abf1afac6064..97de6ad7f9db 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -87,7 +87,7 @@ static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
 				 struct platform_device *pdev)
 {
 	struct dw_pcie *pci = dw_plat_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = &pdev->dev;
 	int ret;
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 13bffa3eaed6..32df3ebccf19 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -155,8 +155,8 @@
 #define MAX_IATU_IN			256
 #define MAX_IATU_OUT			256
 
-struct pcie_port;
 struct dw_pcie;
+struct dw_pcie_rp;
 struct dw_pcie_ep;
 
 enum dw_pcie_region_type {
@@ -173,11 +173,11 @@ enum dw_pcie_device_mode {
 };
 
 struct dw_pcie_host_ops {
-	int (*host_init)(struct pcie_port *pp);
-	int (*msi_host_init)(struct pcie_port *pp);
+	int (*host_init)(struct dw_pcie_rp *pp);
+	int (*msi_host_init)(struct dw_pcie_rp *pp);
 };
 
-struct pcie_port {
+struct dw_pcie_rp {
 	bool			has_msi_ctrl:1;
 	bool			cfg0_io_shared:1;
 	u64			cfg0_base;
@@ -267,7 +267,7 @@ struct dw_pcie {
 	size_t			atu_size;
 	u32			num_ib_windows;
 	u32			num_ob_windows;
-	struct pcie_port	pp;
+	struct dw_pcie_rp	pp;
 	struct dw_pcie_ep	ep;
 	const struct dw_pcie_ops *ops;
 	unsigned int		version;
@@ -380,33 +380,33 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci)
 }
 
 #ifdef CONFIG_PCIE_DW_HOST
-irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
-void dw_pcie_setup_rc(struct pcie_port *pp);
-int dw_pcie_host_init(struct pcie_port *pp);
-void dw_pcie_host_deinit(struct pcie_port *pp);
-int dw_pcie_allocate_domains(struct pcie_port *pp);
+irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
+void dw_pcie_setup_rc(struct dw_pcie_rp *pp);
+int dw_pcie_host_init(struct dw_pcie_rp *pp);
+void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
+int dw_pcie_allocate_domains(struct dw_pcie_rp *pp);
 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
 				       int where);
 #else
-static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
+static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
 {
 	return IRQ_NONE;
 }
 
-static inline void dw_pcie_setup_rc(struct pcie_port *pp)
+static inline void dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 {
 }
 
-static inline int dw_pcie_host_init(struct pcie_port *pp)
+static inline int dw_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	return 0;
 }
 
-static inline void dw_pcie_host_deinit(struct pcie_port *pp)
+static inline void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
 {
 }
 
-static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
+static inline int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
 {
 	return 0;
 }
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 8c5bb9d7cc36..c1e7653e508e 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -186,7 +186,7 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
 	return 0;
 }
 
-static int rockchip_pcie_host_init(struct pcie_port *pp)
+static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
@@ -288,7 +288,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct rockchip_pcie *rockchip;
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 	int ret;
 
 	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c
index 02cc70d8cc06..da059f1c9e92 100644
--- a/drivers/pci/controller/dwc/pcie-fu740.c
+++ b/drivers/pci/controller/dwc/pcie-fu740.c
@@ -236,7 +236,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci)
 	return ret;
 }
 
-static int fu740_pcie_host_init(struct pcie_port *pp)
+static int fu740_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct fu740_pcie *afp = to_fu740_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
index 410555dccb6d..e2b80f10030d 100644
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -74,7 +74,7 @@ static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val)
 	writel(val, histb_pcie->ctrl + reg);
 }
 
-static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
+static void histb_pcie_dbi_w_mode(struct dw_pcie_rp *pp, bool enable)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct histb_pcie *hipcie = to_histb_pcie(pci);
@@ -88,7 +88,7 @@ static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
 	histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val);
 }
 
-static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable)
+static void histb_pcie_dbi_r_mode(struct dw_pcie_rp *pp, bool enable)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct histb_pcie *hipcie = to_histb_pcie(pci);
@@ -180,7 +180,7 @@ static int histb_pcie_start_link(struct dw_pcie *pci)
 	return 0;
 }
 
-static int histb_pcie_host_init(struct pcie_port *pp)
+static int histb_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct histb_pcie *hipcie = to_histb_pcie(pci);
@@ -219,7 +219,7 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie)
 		regulator_disable(hipcie->vpcie);
 }
 
-static int histb_pcie_host_enable(struct pcie_port *pp)
+static int histb_pcie_host_enable(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct histb_pcie *hipcie = to_histb_pcie(pci);
@@ -297,7 +297,7 @@ static int histb_pcie_probe(struct platform_device *pdev)
 {
 	struct histb_pcie *hipcie;
 	struct dw_pcie *pci;
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 	struct device_node *np = pdev->dev.of_node;
 	struct device *dev = &pdev->dev;
 	enum of_gpio_flags of_flags;
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 5ba144924ff8..07bc54886d71 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -343,7 +343,7 @@ static void __intel_pcie_remove(struct intel_pcie *pcie)
 static int intel_pcie_remove(struct platform_device *pdev)
 {
 	struct intel_pcie *pcie = platform_get_drvdata(pdev);
-	struct pcie_port *pp = &pcie->pci.pp;
+	struct dw_pcie_rp *pp = &pcie->pci.pp;
 
 	dw_pcie_host_deinit(pp);
 	__intel_pcie_remove(pcie);
@@ -373,7 +373,7 @@ static int __maybe_unused intel_pcie_resume_noirq(struct device *dev)
 	return intel_pcie_host_setup(pcie);
 }
 
-static int intel_pcie_rc_init(struct pcie_port *pp)
+static int intel_pcie_rc_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct intel_pcie *pcie = dev_get_drvdata(pci->dev);
@@ -403,7 +403,7 @@ static int intel_pcie_probe(struct platform_device *pdev)
 	const struct intel_pcie_soc *data;
 	struct device *dev = &pdev->dev;
 	struct intel_pcie *pcie;
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 	struct dw_pcie *pci;
 	int ret;
 
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index 1ac29a6eef22..58f3caf75cff 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -231,7 +231,7 @@ static void keembay_pcie_msi_irq_handler(struct irq_desc *desc)
 	struct keembay_pcie *pcie = irq_desc_get_handler_data(desc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	u32 val, mask, status;
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 
 	/*
 	 * Keem Bay PCIe Controller provides an additional IP logic on top of
@@ -332,7 +332,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
 				      struct platform_device *pdev)
 {
 	struct dw_pcie *pci = &pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = &pdev->dev;
 	u32 val;
 	int ret;
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index a52cad269f85..7f67aad71df4 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -620,7 +620,7 @@ static int kirin_pcie_start_link(struct dw_pcie *pci)
 	return 0;
 }
 
-static int kirin_pcie_host_init(struct pcie_port *pp)
+static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	pp->bridge->ops = &kirin_pci_ops;
 
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2ea13750b492..a9b2322624d5 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1381,7 +1381,7 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
 	return 0;
 }
 
-static int qcom_pcie_host_init(struct pcie_port *pp)
+static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
@@ -1564,7 +1564,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 static int qcom_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 	struct dw_pcie *pci;
 	struct qcom_pcie *pcie;
 	const struct qcom_pcie_cfg *pcie_cfg;
diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
index 1569e82b5568..7fd698da144e 100644
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -85,7 +85,7 @@ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
 	struct spear13xx_pcie *spear13xx_pcie = arg;
 	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
 	struct dw_pcie *pci = spear13xx_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	unsigned int status;
 
 	status = readl(&app_reg->int_sts);
@@ -121,7 +121,7 @@ static int spear13xx_pcie_link_up(struct dw_pcie *pci)
 	return 0;
 }
 
-static int spear13xx_pcie_host_init(struct pcie_port *pp)
+static int spear13xx_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
@@ -155,7 +155,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
 				   struct platform_device *pdev)
 {
 	struct dw_pcie *pci = spear13xx_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	struct device *dev = &pdev->dev;
 	int ret;
 
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index cc2678490162..65135f5c4a4a 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -311,7 +311,7 @@ struct tegra_pcie_soc {
 	enum dw_pcie_device_mode mode;
 };
 
-static void apply_bad_link_workaround(struct pcie_port *pp)
+static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
@@ -349,7 +349,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
 {
 	struct tegra194_pcie *pcie = arg;
 	struct dw_pcie *pci = &pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	u32 val, tmp;
 	u16 val_w;
 
@@ -698,7 +698,7 @@ static inline void init_host_aspm(struct tegra194_pcie *pcie) { return; }
 static inline void init_debugfs(struct tegra194_pcie *pcie) { return; }
 #endif
 
-static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
+static void tegra_pcie_enable_system_interrupts(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
@@ -736,7 +736,7 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
 			   val_w);
 }
 
-static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
+static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
@@ -757,7 +757,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
 	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
 }
 
-static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
+static void tegra_pcie_enable_msi_interrupts(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
@@ -770,7 +770,7 @@ static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
 	appl_writel(pcie, val, APPL_INTR_EN_L0_0);
 }
 
-static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
+static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
@@ -851,7 +851,7 @@ static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)
 	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
 }
 
-static int tegra194_pcie_host_init(struct pcie_port *pp)
+static int tegra194_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
@@ -916,7 +916,7 @@ static int tegra194_pcie_start_link(struct dw_pcie *pci)
 {
 	u32 val, offset, speed, tmp;
 	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	bool retry = true;
 
 	if (pcie->mode == DW_PCIE_EP_TYPE) {
@@ -1212,7 +1212,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie,
 
 static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)
 {
-	struct pcie_port *pp = &pcie->pci.pp;
+	struct dw_pcie_rp *pp = &pcie->pci.pp;
 	struct pci_bus *child, *root_bus = NULL;
 	struct pci_dev *pdev;
 
@@ -1443,7 +1443,7 @@ static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie)
 static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
 {
 	struct dw_pcie *pci = &pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 	int ret;
 
 	ret = tegra_pcie_config_controller(pcie, false);
@@ -1961,7 +1961,7 @@ static int tegra194_pcie_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct resource *atu_dma_res;
 	struct tegra194_pcie *pcie;
-	struct pcie_port *pp;
+	struct dw_pcie_rp *pp;
 	struct dw_pcie *pci;
 	struct phy **phys;
 	char *name;
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
index b45ac3754242..48c3eba817b4 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -171,7 +171,7 @@ static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie)
 
 static void uniphier_pcie_irq_mask(struct irq_data *d)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
 	unsigned long flags;
@@ -188,7 +188,7 @@ static void uniphier_pcie_irq_mask(struct irq_data *d)
 
 static void uniphier_pcie_irq_unmask(struct irq_data *d)
 {
-	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
 	unsigned long flags;
@@ -225,7 +225,7 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = {
 
 static void uniphier_pcie_irq_handler(struct irq_desc *desc)
 {
-	struct pcie_port *pp = irq_desc_get_handler_data(desc);
+	struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
@@ -258,7 +258,7 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
+static int uniphier_pcie_config_legacy_irq(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
@@ -295,7 +295,7 @@ static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
 	return ret;
 }
 
-static int uniphier_pcie_host_init(struct pcie_port *pp)
+static int uniphier_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
index 50f80f07e4db..71026fefa366 100644
--- a/drivers/pci/controller/dwc/pcie-visconti.c
+++ b/drivers/pci/controller/dwc/pcie-visconti.c
@@ -178,7 +178,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
  */
 static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
 {
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 
 	return cpu_addr & ~pp->io_base;
 }
@@ -190,7 +190,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 	.stop_link = visconti_pcie_stop_link,
 };
 
-static int visconti_pcie_host_init(struct pcie_port *pp)
+static int visconti_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
@@ -278,7 +278,7 @@ static int visconti_add_pcie_port(struct visconti_pcie *pcie,
 				  struct platform_device *pdev)
 {
 	struct dw_pcie *pci = &pcie->pci;
-	struct pcie_port *pp = &pci->pp;
+	struct dw_pcie_rp *pp = &pci->pp;
 
 	pp->irq = platform_get_irq_byname(pdev, "intr");
 	if (pp->irq < 0)
-- 
2.35.1

[PATCH RESEND v5 16/18] PCI: dwc-plat: Simplify the probe method return value handling

[Serge Semin]

The whole switch-case-logic implemented in the DWC PCIe RC/EP probe
procedure doesn't seem well thought through. First of all the ret variable
is unused in the EP-case and is only partly involved in the RC-case of the
switch-case statement, which unnecessary complicates the code. Secondly
the probe method will return zero if an unknown mode is detected. That is
improbable situation since the OF-device data is initialized only with
valid modes, but such code is still wrong at least from maintainability
point of view. So let's convert the switch-case part of the probe function
to being more coherent. We suggest to use the local ret variable to
preserve the status of the case-clauses and return its value from the
probe procedure after the work is done.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-plat.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 97de6ad7f9db..c6871bebf3fe 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -143,20 +143,21 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
 			return -ENODEV;
 
 		ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
-		if (ret < 0)
-			return ret;
 		break;
 	case DW_PCIE_EP_TYPE:
 		if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
 			return -ENODEV;
 
 		pci->ep.ops = &pcie_ep_ops;
-		return dw_pcie_ep_init(&pci->ep);
+		ret = dw_pcie_ep_init(&pci->ep);
+		break;
 	default:
 		dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
+		ret = -EINVAL;
+		break;
 	}
 
-	return 0;
+	return ret;
 }
 
 static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
-- 
2.35.1

[PATCH RESEND v5 17/18] PCI: dwc-plat: Discard unused regmap pointer

[Serge Semin]

The regmap pointer was added into the dw_plat_pcie structure in
commit 1d906b22076e ("PCI: dwc: Add support for EP mode"), but it hasn't
been utilized neither in the code submitted in the denoted so far nor in
the platform driver evolving afterwards. Drop it then for good.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-plat.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index c6871bebf3fe..59bd85d4190b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -17,13 +17,11 @@
 #include <linux/platform_device.h>
 #include <linux/resource.h>
 #include <linux/types.h>
-#include <linux/regmap.h>
 
 #include "pcie-designware.h"
 
 struct dw_plat_pcie {
 	struct dw_pcie			*pci;
-	struct regmap			*regmap;
 	enum dw_pcie_device_mode	mode;
 };
 
-- 
2.35.1

[PATCH RESEND v5 18/18] PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration

[Serge Semin]

The denoted forward declaration used to be required to get the OF-device
ID structure by calling the of_match_device() method. The later method
invocation has been replaced with the of_device_get_match_data() call in
the commit 5c204204cf24 ("PCI: designware-plat: Prefer
of_device_get_match_data()"). Thus the forward declaration of the
OF-compatible device strings no longer needed. Drop it for good.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-plat.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 59bd85d4190b..1fcfb840f238 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -29,8 +29,6 @@ struct dw_plat_pcie_of_data {
 	enum dw_pcie_device_mode	mode;
 };
 
-static const struct of_device_id dw_plat_pcie_of_match[];
-
 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
 };
 
-- 
2.35.1

Re: [PATCH RESEND v5 15/18] PCI: dwc: Add dw_ prefix to the pcie_port structure name

[Jesper Nilsson]

On Fri, Jun 24, 2022 at 04:34:25PM +0200, Serge Semin wrote:
> All of the DW PCIe core driver entities have names with the dw_ prefix in
> order to easily distinguish local and common PCIe name spaces. All except
> the pcie_port structure which contains the DW PCIe Root Port descriptor.
> For historical reason the structure has retained the original name since
> commit 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos") when
> the DW PCIe IP-core support was added to the kernel. Let's finally fix
> that by adding the dw_ prefix to the structure name and by adding the _rp
> suffix to be similar to the EP counterpart. Thus the name will be coherent
> with the common driver naming policy. It shall make the driver code more
> readable eliminating visual confusion between the local and generic PCI
> name spaces.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>

Sorry, I never replied in the thread for the last patch,
your reasoning for not changing the parameter name made sense.

For the ARTPEC-6 parts,

Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>

/^JN - Jesper Nilsson
-- 
               Jesper Nilsson -- jesper.nilsson@axis.com

Re: [PATCH RESEND v5 15/18] PCI: dwc: Add dw_ prefix to the pcie_port structure name

[Neil Armstrong]

On 24/06/2022 16:34, Serge Semin wrote:
> All of the DW PCIe core driver entities have names with the dw_ prefix in
> order to easily distinguish local and common PCIe name spaces. All except
> the pcie_port structure which contains the DW PCIe Root Port descriptor.
> For historical reason the structure has retained the original name since
> commit 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos") when
> the DW PCIe IP-core support was added to the kernel. Let's finally fix
> that by adding the dw_ prefix to the structure name and by adding the _rp
> suffix to be similar to the EP counterpart. Thus the name will be coherent
> with the common driver naming policy. It shall make the driver code more
> readable eliminating visual confusion between the local and generic PCI
> name spaces.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>   drivers/pci/controller/dwc/pci-dra7xx.c       | 12 +++----
>   drivers/pci/controller/dwc/pci-exynos.c       |  6 ++--
>   drivers/pci/controller/dwc/pci-imx6.c         |  6 ++--
>   drivers/pci/controller/dwc/pci-keystone.c     | 20 +++++------
>   drivers/pci/controller/dwc/pci-layerscape.c   |  2 +-
>   drivers/pci/controller/dwc/pci-meson.c        |  2 +-
>   drivers/pci/controller/dwc/pcie-al.c          |  6 ++--
>   drivers/pci/controller/dwc/pcie-armada8k.c    |  4 +--
>   drivers/pci/controller/dwc/pcie-artpec6.c     |  4 +--
>   .../pci/controller/dwc/pcie-designware-host.c | 36 +++++++++----------
>   .../pci/controller/dwc/pcie-designware-plat.c |  2 +-
>   drivers/pci/controller/dwc/pcie-designware.h  | 30 ++++++++--------
>   drivers/pci/controller/dwc/pcie-dw-rockchip.c |  4 +--
>   drivers/pci/controller/dwc/pcie-fu740.c       |  2 +-
>   drivers/pci/controller/dwc/pcie-histb.c       | 10 +++---
>   drivers/pci/controller/dwc/pcie-intel-gw.c    |  6 ++--
>   drivers/pci/controller/dwc/pcie-keembay.c     |  4 +--
>   drivers/pci/controller/dwc/pcie-kirin.c       |  2 +-
>   drivers/pci/controller/dwc/pcie-qcom.c        |  4 +--
>   drivers/pci/controller/dwc/pcie-spear13xx.c   |  6 ++--
>   drivers/pci/controller/dwc/pcie-tegra194.c    | 22 ++++++------
>   drivers/pci/controller/dwc/pcie-uniphier.c    | 10 +++---
>   drivers/pci/controller/dwc/pcie-visconti.c    |  6 ++--
>   23 files changed, 103 insertions(+), 103 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index dfcdeb432dc8..a174b680b2a7 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -178,7 +178,7 @@ static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
>   	dra7xx_pcie_enable_msi_interrupts(dra7xx);
>   }
>   
> -static int dra7xx_pcie_host_init(struct pcie_port *pp)
> +static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> @@ -202,7 +202,7 @@ static const struct irq_domain_ops intx_domain_ops = {
>   	.xlate = pci_irqd_intx_xlate,
>   };
>   
> -static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
> +static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	unsigned long val;
> @@ -224,7 +224,7 @@ static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
>   	return 1;
>   }
>   
> -static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
> +static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	int ret, i, count, num_ctrls;
> @@ -255,8 +255,8 @@ static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
>   {
>   	struct irq_chip *chip = irq_desc_get_chip(desc);
>   	struct dra7xx_pcie *dra7xx;
> +	struct dw_pcie_rp *pp;
>   	struct dw_pcie *pci;
> -	struct pcie_port *pp;
>   	unsigned long reg;
>   	u32 bit;
>   
> @@ -344,7 +344,7 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
>   	return IRQ_HANDLED;
>   }
>   
> -static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
> +static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct device *dev = pci->dev;
> @@ -475,7 +475,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
>   {
>   	int ret;
>   	struct dw_pcie *pci = dra7xx->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = pci->dev;
>   
>   	pp->irq = platform_get_irq(pdev, 1);
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index 467c8d1cd7e4..2044d191fba6 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -249,7 +249,7 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
>   	return (val & PCIE_ELBI_XMLH_LINKUP);
>   }
>   
> -static int exynos_pcie_host_init(struct pcie_port *pp)
> +static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct exynos_pcie *ep = to_exynos_pcie(pci);
> @@ -276,7 +276,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep,
>   				       struct platform_device *pdev)
>   {
>   	struct dw_pcie *pci = &ep->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = &pdev->dev;
>   	int ret;
>   
> @@ -406,7 +406,7 @@ static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
>   {
>   	struct exynos_pcie *ep = dev_get_drvdata(dev);
>   	struct dw_pcie *pci = &ep->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	int ret;
>   
>   	ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 7a285fb0f619..5ea01ed4674d 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -863,7 +863,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
>   	return ret;
>   }
>   
> -static int imx6_pcie_host_init(struct pcie_port *pp)
> +static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> @@ -992,7 +992,7 @@ static int imx6_pcie_resume_noirq(struct device *dev)
>   {
>   	int ret;
>   	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> -	struct pcie_port *pp = &imx6_pcie->pci->pp;
> +	struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
>   
>   	if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
>   		return 0;
> @@ -1291,7 +1291,7 @@ static struct platform_driver imx6_pcie_driver = {
>   static void imx6_pcie_quirk(struct pci_dev *dev)
>   {
>   	struct pci_bus *bus = dev->bus;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   
>   	/* Bus parent is the PCI bridge, its parent is this platform driver */
>   	if (!bus->dev.parent || !bus->dev.parent->parent)
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index d10e5fd0f83c..c3d88aa27dd4 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -147,7 +147,7 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
>   
>   static void ks_pcie_msi_irq_ack(struct irq_data *data)
>   {
> -	struct pcie_port *pp  = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(data);
>   	struct keystone_pcie *ks_pcie;
>   	u32 irq = data->hwirq;
>   	struct dw_pcie *pci;
> @@ -167,7 +167,7 @@ static void ks_pcie_msi_irq_ack(struct irq_data *data)
>   
>   static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
>   	struct keystone_pcie *ks_pcie;
>   	struct dw_pcie *pci;
>   	u64 msi_target;
> @@ -192,7 +192,7 @@ static int ks_pcie_msi_set_affinity(struct irq_data *irq_data,
>   
>   static void ks_pcie_msi_mask(struct irq_data *data)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
>   	struct keystone_pcie *ks_pcie;
>   	u32 irq = data->hwirq;
>   	struct dw_pcie *pci;
> @@ -216,7 +216,7 @@ static void ks_pcie_msi_mask(struct irq_data *data)
>   
>   static void ks_pcie_msi_unmask(struct irq_data *data)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
>   	struct keystone_pcie *ks_pcie;
>   	u32 irq = data->hwirq;
>   	struct dw_pcie *pci;
> @@ -247,7 +247,7 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
>   	.irq_unmask = ks_pcie_msi_unmask,
>   };
>   
> -static int ks_pcie_msi_host_init(struct pcie_port *pp)
> +static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
>   {
>   	pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
>   	return dw_pcie_allocate_domains(pp);
> @@ -390,7 +390,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>   	u32 val;
>   	u32 num_viewport = ks_pcie->num_viewport;
>   	struct dw_pcie *pci = ks_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	u64 start, end;
>   	struct resource *mem;
>   	int i;
> @@ -428,7 +428,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>   static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
>   					   unsigned int devfn, int where)
>   {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>   	u32 reg;
> @@ -456,7 +456,7 @@ static struct pci_ops ks_child_pcie_ops = {
>    */
>   static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
>   {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>   
> @@ -574,7 +574,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
>   	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
>   	u32 offset = irq - ks_pcie->msi_host_irq;
>   	struct dw_pcie *pci = ks_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = pci->dev;
>   	struct irq_chip *chip = irq_desc_get_chip(desc);
>   	u32 vector, reg, pos;
> @@ -799,7 +799,7 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
>   	return 0;
>   }
>   
> -static int __init ks_pcie_host_init(struct pcie_port *pp)
> +static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
> index 6a4f0619bb1c..879b8692f96a 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape.c
> @@ -74,7 +74,7 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
>   	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
>   }
>   
> -static int ls_pcie_host_init(struct pcie_port *pp)
> +static int ls_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct ls_pcie *pcie = to_ls_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
> index f44bf347904a..c1527693bed9 100644
> --- a/drivers/pci/controller/dwc/pci-meson.c
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -370,7 +370,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci)
>   	return 0;
>   }
>   
> -static int meson_pcie_host_init(struct pcie_port *pp)
> +static int meson_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct meson_pcie *mp = to_meson_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c
> index e8afa50129a8..b8cb77c9c4bd 100644
> --- a/drivers/pci/controller/dwc/pcie-al.c
> +++ b/drivers/pci/controller/dwc/pcie-al.c
> @@ -217,7 +217,7 @@ static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
>   static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus,
>   					       unsigned int devfn, int where)
>   {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
>   	unsigned int busnr = bus->number;
>   	struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
> @@ -245,7 +245,7 @@ static struct pci_ops al_child_pci_ops = {
>   static void al_pcie_config_prepare(struct al_pcie *pcie)
>   {
>   	struct al_pcie_target_bus_cfg *target_bus_cfg;
> -	struct pcie_port *pp = &pcie->pci->pp;
> +	struct dw_pcie_rp *pp = &pcie->pci->pp;
>   	unsigned int ecam_bus_mask;
>   	u32 cfg_control_offset;
>   	u8 subordinate_bus;
> @@ -289,7 +289,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie)
>   	al_pcie_controller_writel(pcie, cfg_control_offset, reg);
>   }
>   
> -static int al_pcie_host_init(struct pcie_port *pp)
> +static int al_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct al_pcie *pcie = to_al_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
> index 4e2552dcf982..8b113d3f3095 100644
> --- a/drivers/pci/controller/dwc/pcie-armada8k.c
> +++ b/drivers/pci/controller/dwc/pcie-armada8k.c
> @@ -166,7 +166,7 @@ static int armada8k_pcie_start_link(struct dw_pcie *pci)
>   	return 0;
>   }
>   
> -static int armada8k_pcie_host_init(struct pcie_port *pp)
> +static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	u32 reg;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -233,7 +233,7 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
>   				  struct platform_device *pdev)
>   {
>   	struct dw_pcie *pci = pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = &pdev->dev;
>   	int ret;
>   
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index 2f15441770e1..98102079e26d 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -97,7 +97,7 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
>   static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
>   {
>   	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct dw_pcie_ep *ep = &pci->ep;
>   
>   	switch (artpec6_pcie->mode) {
> @@ -315,7 +315,7 @@ static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
>   	usleep_range(100, 200);
>   }
>   
> -static int artpec6_pcie_host_init(struct pcie_port *pp)
> +static int artpec6_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 7ff2b7555b91..95256434913f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -53,7 +53,7 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
>   };
>   
>   /* MSI int handler */
> -irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> +irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
>   {
>   	int i, pos;
>   	unsigned long val;
> @@ -88,7 +88,7 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>   static void dw_chained_msi_isr(struct irq_desc *desc)
>   {
>   	struct irq_chip *chip = irq_desc_get_chip(desc);
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   
>   	chained_irq_enter(chip, desc);
>   
> @@ -100,7 +100,7 @@ static void dw_chained_msi_isr(struct irq_desc *desc)
>   
>   static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	u64 msi_target;
>   
> @@ -123,7 +123,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d,
>   
>   static void dw_pci_bottom_mask(struct irq_data *d)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	unsigned int res, bit, ctrl;
>   	unsigned long flags;
> @@ -142,7 +142,7 @@ static void dw_pci_bottom_mask(struct irq_data *d)
>   
>   static void dw_pci_bottom_unmask(struct irq_data *d)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	unsigned int res, bit, ctrl;
>   	unsigned long flags;
> @@ -161,7 +161,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d)
>   
>   static void dw_pci_bottom_ack(struct irq_data *d)
>   {
> -	struct pcie_port *pp  = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(d);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	unsigned int res, bit, ctrl;
>   
> @@ -185,7 +185,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
>   				    unsigned int virq, unsigned int nr_irqs,
>   				    void *args)
>   {
> -	struct pcie_port *pp = domain->host_data;
> +	struct dw_pcie_rp *pp = domain->host_data;
>   	unsigned long flags;
>   	u32 i;
>   	int bit;
> @@ -213,7 +213,7 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain,
>   				    unsigned int virq, unsigned int nr_irqs)
>   {
>   	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> -	struct pcie_port *pp = domain->host_data;
> +	struct dw_pcie_rp *pp = domain->host_data;
>   	unsigned long flags;
>   
>   	raw_spin_lock_irqsave(&pp->lock, flags);
> @@ -229,7 +229,7 @@ static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
>   	.free	= dw_pcie_irq_domain_free,
>   };
>   
> -int dw_pcie_allocate_domains(struct pcie_port *pp)
> +int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
> @@ -255,7 +255,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
>   	return 0;
>   }
>   
> -static void dw_pcie_free_msi(struct pcie_port *pp)
> +static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
>   {
>   	if (pp->msi_irq)
>   		irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
> @@ -272,7 +272,7 @@ static void dw_pcie_free_msi(struct pcie_port *pp)
>   	}
>   }
>   
> -static void dw_pcie_msi_init(struct pcie_port *pp)
> +static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	u64 msi_target = (u64)pp->msi_data;
> @@ -285,7 +285,7 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
>   	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
>   }
>   
> -int dw_pcie_host_init(struct pcie_port *pp)
> +int dw_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct device *dev = pci->dev;
> @@ -436,7 +436,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>   }
>   EXPORT_SYMBOL_GPL(dw_pcie_host_init);
>   
> -void dw_pcie_host_deinit(struct pcie_port *pp)
> +void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   
> @@ -455,7 +455,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
>   {
>   	int type;
>   	u32 busdev;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   
>   	/*
> @@ -487,7 +487,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
>   				 int where, int size, u32 *val)
>   {
>   	int ret;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   
>   	ret = pci_generic_config_read(bus, devfn, where, size, val);
> @@ -503,7 +503,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
>   				 int where, int size, u32 val)
>   {
>   	int ret;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   
>   	ret = pci_generic_config_write(bus, devfn, where, size, val);
> @@ -523,7 +523,7 @@ static struct pci_ops dw_child_pcie_ops = {
>   
>   void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
>   {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   
>   	if (PCI_SLOT(devfn) > 0)
> @@ -539,7 +539,7 @@ static struct pci_ops dw_pcie_ops = {
>   	.write = pci_generic_config_write,
>   };
>   
> -void dw_pcie_setup_rc(struct pcie_port *pp)
> +void dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>   {
>   	u32 val, ctrl, num_ctrls;
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index abf1afac6064..97de6ad7f9db 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -87,7 +87,7 @@ static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
>   				 struct platform_device *pdev)
>   {
>   	struct dw_pcie *pci = dw_plat_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = &pdev->dev;
>   	int ret;
>   
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 13bffa3eaed6..32df3ebccf19 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -155,8 +155,8 @@
>   #define MAX_IATU_IN			256
>   #define MAX_IATU_OUT			256
>   
> -struct pcie_port;
>   struct dw_pcie;
> +struct dw_pcie_rp;
>   struct dw_pcie_ep;
>   
>   enum dw_pcie_region_type {
> @@ -173,11 +173,11 @@ enum dw_pcie_device_mode {
>   };
>   
>   struct dw_pcie_host_ops {
> -	int (*host_init)(struct pcie_port *pp);
> -	int (*msi_host_init)(struct pcie_port *pp);
> +	int (*host_init)(struct dw_pcie_rp *pp);
> +	int (*msi_host_init)(struct dw_pcie_rp *pp);
>   };
>   
> -struct pcie_port {
> +struct dw_pcie_rp {
>   	bool			has_msi_ctrl:1;
>   	bool			cfg0_io_shared:1;
>   	u64			cfg0_base;
> @@ -267,7 +267,7 @@ struct dw_pcie {
>   	size_t			atu_size;
>   	u32			num_ib_windows;
>   	u32			num_ob_windows;
> -	struct pcie_port	pp;
> +	struct dw_pcie_rp	pp;
>   	struct dw_pcie_ep	ep;
>   	const struct dw_pcie_ops *ops;
>   	unsigned int		version;
> @@ -380,33 +380,33 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci)
>   }
>   
>   #ifdef CONFIG_PCIE_DW_HOST
> -irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
> -void dw_pcie_setup_rc(struct pcie_port *pp);
> -int dw_pcie_host_init(struct pcie_port *pp);
> -void dw_pcie_host_deinit(struct pcie_port *pp);
> -int dw_pcie_allocate_domains(struct pcie_port *pp);
> +irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
> +void dw_pcie_setup_rc(struct dw_pcie_rp *pp);
> +int dw_pcie_host_init(struct dw_pcie_rp *pp);
> +void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
> +int dw_pcie_allocate_domains(struct dw_pcie_rp *pp);
>   void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
>   				       int where);
>   #else
> -static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> +static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
>   {
>   	return IRQ_NONE;
>   }
>   
> -static inline void dw_pcie_setup_rc(struct pcie_port *pp)
> +static inline void dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>   {
>   }
>   
> -static inline int dw_pcie_host_init(struct pcie_port *pp)
> +static inline int dw_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	return 0;
>   }
>   
> -static inline void dw_pcie_host_deinit(struct pcie_port *pp)
> +static inline void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
>   {
>   }
>   
> -static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
> +static inline int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
>   {
>   	return 0;
>   }
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 8c5bb9d7cc36..c1e7653e508e 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -186,7 +186,7 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
>   	return 0;
>   }
>   
> -static int rockchip_pcie_host_init(struct pcie_port *pp)
> +static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> @@ -288,7 +288,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
>   	struct rockchip_pcie *rockchip;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   	int ret;
>   
>   	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
> diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c
> index 02cc70d8cc06..da059f1c9e92 100644
> --- a/drivers/pci/controller/dwc/pcie-fu740.c
> +++ b/drivers/pci/controller/dwc/pcie-fu740.c
> @@ -236,7 +236,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci)
>   	return ret;
>   }
>   
> -static int fu740_pcie_host_init(struct pcie_port *pp)
> +static int fu740_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct fu740_pcie *afp = to_fu740_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
> index 410555dccb6d..e2b80f10030d 100644
> --- a/drivers/pci/controller/dwc/pcie-histb.c
> +++ b/drivers/pci/controller/dwc/pcie-histb.c
> @@ -74,7 +74,7 @@ static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val)
>   	writel(val, histb_pcie->ctrl + reg);
>   }
>   
> -static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
> +static void histb_pcie_dbi_w_mode(struct dw_pcie_rp *pp, bool enable)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -88,7 +88,7 @@ static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
>   	histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val);
>   }
>   
> -static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable)
> +static void histb_pcie_dbi_r_mode(struct dw_pcie_rp *pp, bool enable)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -180,7 +180,7 @@ static int histb_pcie_start_link(struct dw_pcie *pci)
>   	return 0;
>   }
>   
> -static int histb_pcie_host_init(struct pcie_port *pp)
> +static int histb_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -219,7 +219,7 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie)
>   		regulator_disable(hipcie->vpcie);
>   }
>   
> -static int histb_pcie_host_enable(struct pcie_port *pp)
> +static int histb_pcie_host_enable(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -297,7 +297,7 @@ static int histb_pcie_probe(struct platform_device *pdev)
>   {
>   	struct histb_pcie *hipcie;
>   	struct dw_pcie *pci;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   	struct device_node *np = pdev->dev.of_node;
>   	struct device *dev = &pdev->dev;
>   	enum of_gpio_flags of_flags;
> diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
> index 5ba144924ff8..07bc54886d71 100644
> --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
> +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
> @@ -343,7 +343,7 @@ static void __intel_pcie_remove(struct intel_pcie *pcie)
>   static int intel_pcie_remove(struct platform_device *pdev)
>   {
>   	struct intel_pcie *pcie = platform_get_drvdata(pdev);
> -	struct pcie_port *pp = &pcie->pci.pp;
> +	struct dw_pcie_rp *pp = &pcie->pci.pp;
>   
>   	dw_pcie_host_deinit(pp);
>   	__intel_pcie_remove(pcie);
> @@ -373,7 +373,7 @@ static int __maybe_unused intel_pcie_resume_noirq(struct device *dev)
>   	return intel_pcie_host_setup(pcie);
>   }
>   
> -static int intel_pcie_rc_init(struct pcie_port *pp)
> +static int intel_pcie_rc_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct intel_pcie *pcie = dev_get_drvdata(pci->dev);
> @@ -403,7 +403,7 @@ static int intel_pcie_probe(struct platform_device *pdev)
>   	const struct intel_pcie_soc *data;
>   	struct device *dev = &pdev->dev;
>   	struct intel_pcie *pcie;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   	struct dw_pcie *pci;
>   	int ret;
>   
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 1ac29a6eef22..58f3caf75cff 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -231,7 +231,7 @@ static void keembay_pcie_msi_irq_handler(struct irq_desc *desc)
>   	struct keembay_pcie *pcie = irq_desc_get_handler_data(desc);
>   	struct irq_chip *chip = irq_desc_get_chip(desc);
>   	u32 val, mask, status;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   
>   	/*
>   	 * Keem Bay PCIe Controller provides an additional IP logic on top of
> @@ -332,7 +332,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
>   				      struct platform_device *pdev)
>   {
>   	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = &pdev->dev;
>   	u32 val;
>   	int ret;
> diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
> index a52cad269f85..7f67aad71df4 100644
> --- a/drivers/pci/controller/dwc/pcie-kirin.c
> +++ b/drivers/pci/controller/dwc/pcie-kirin.c
> @@ -620,7 +620,7 @@ static int kirin_pcie_start_link(struct dw_pcie *pci)
>   	return 0;
>   }
>   
> -static int kirin_pcie_host_init(struct pcie_port *pp)
> +static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	pp->bridge->ops = &kirin_pci_ops;
>   
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 2ea13750b492..a9b2322624d5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1381,7 +1381,7 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
>   	return 0;
>   }
>   
> -static int qcom_pcie_host_init(struct pcie_port *pp)
> +static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct qcom_pcie *pcie = to_qcom_pcie(pci);
> @@ -1564,7 +1564,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
>   static int qcom_pcie_probe(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   	struct dw_pcie *pci;
>   	struct qcom_pcie *pcie;
>   	const struct qcom_pcie_cfg *pcie_cfg;
> diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
> index 1569e82b5568..7fd698da144e 100644
> --- a/drivers/pci/controller/dwc/pcie-spear13xx.c
> +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
> @@ -85,7 +85,7 @@ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
>   	struct spear13xx_pcie *spear13xx_pcie = arg;
>   	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
>   	struct dw_pcie *pci = spear13xx_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	unsigned int status;
>   
>   	status = readl(&app_reg->int_sts);
> @@ -121,7 +121,7 @@ static int spear13xx_pcie_link_up(struct dw_pcie *pci)
>   	return 0;
>   }
>   
> -static int spear13xx_pcie_host_init(struct pcie_port *pp)
> +static int spear13xx_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
> @@ -155,7 +155,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
>   				   struct platform_device *pdev)
>   {
>   	struct dw_pcie *pci = spear13xx_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	struct device *dev = &pdev->dev;
>   	int ret;
>   
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index cc2678490162..65135f5c4a4a 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -311,7 +311,7 @@ struct tegra_pcie_soc {
>   	enum dw_pcie_device_mode mode;
>   };
>   
> -static void apply_bad_link_workaround(struct pcie_port *pp)
> +static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -349,7 +349,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
>   {
>   	struct tegra194_pcie *pcie = arg;
>   	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	u32 val, tmp;
>   	u16 val_w;
>   
> @@ -698,7 +698,7 @@ static inline void init_host_aspm(struct tegra194_pcie *pcie) { return; }
>   static inline void init_debugfs(struct tegra194_pcie *pcie) { return; }
>   #endif
>   
> -static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_system_interrupts(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -736,7 +736,7 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
>   			   val_w);
>   }
>   
> -static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -757,7 +757,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
>   	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
>   }
>   
> -static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_msi_interrupts(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -770,7 +770,7 @@ static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
>   	appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>   }
>   
> -static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -851,7 +851,7 @@ static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)
>   	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>   }
>   
> -static int tegra194_pcie_host_init(struct pcie_port *pp)
> +static int tegra194_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -916,7 +916,7 @@ static int tegra194_pcie_start_link(struct dw_pcie *pci)
>   {
>   	u32 val, offset, speed, tmp;
>   	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	bool retry = true;
>   
>   	if (pcie->mode == DW_PCIE_EP_TYPE) {
> @@ -1212,7 +1212,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie,
>   
>   static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)
>   {
> -	struct pcie_port *pp = &pcie->pci.pp;
> +	struct dw_pcie_rp *pp = &pcie->pci.pp;
>   	struct pci_bus *child, *root_bus = NULL;
>   	struct pci_dev *pdev;
>   
> @@ -1443,7 +1443,7 @@ static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie)
>   static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
>   {
>   	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   	int ret;
>   
>   	ret = tegra_pcie_config_controller(pcie, false);
> @@ -1961,7 +1961,7 @@ static int tegra194_pcie_probe(struct platform_device *pdev)
>   	struct device *dev = &pdev->dev;
>   	struct resource *atu_dma_res;
>   	struct tegra194_pcie *pcie;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>   	struct dw_pcie *pci;
>   	struct phy **phys;
>   	char *name;
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
> index b45ac3754242..48c3eba817b4 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
> @@ -171,7 +171,7 @@ static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie)
>   
>   static void uniphier_pcie_irq_mask(struct irq_data *d)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
>   	unsigned long flags;
> @@ -188,7 +188,7 @@ static void uniphier_pcie_irq_mask(struct irq_data *d)
>   
>   static void uniphier_pcie_irq_unmask(struct irq_data *d)
>   {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
>   	unsigned long flags;
> @@ -225,7 +225,7 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = {
>   
>   static void uniphier_pcie_irq_handler(struct irq_desc *desc)
>   {
> -	struct pcie_port *pp = irq_desc_get_handler_data(desc);
> +	struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
>   	struct irq_chip *chip = irq_desc_get_chip(desc);
> @@ -258,7 +258,7 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)
>   	chained_irq_exit(chip, desc);
>   }
>   
> -static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
> +static int uniphier_pcie_config_legacy_irq(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
> @@ -295,7 +295,7 @@ static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
>   	return ret;
>   }
>   
> -static int uniphier_pcie_host_init(struct pcie_port *pp)
> +static int uniphier_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
> index 50f80f07e4db..71026fefa366 100644
> --- a/drivers/pci/controller/dwc/pcie-visconti.c
> +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> @@ -178,7 +178,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
>    */
>   static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
>   {
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   
>   	return cpu_addr & ~pp->io_base;
>   }
> @@ -190,7 +190,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
>   	.stop_link = visconti_pcie_stop_link,
>   };
>   
> -static int visconti_pcie_host_init(struct pcie_port *pp)
> +static int visconti_pcie_host_init(struct dw_pcie_rp *pp)
>   {
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
> @@ -278,7 +278,7 @@ static int visconti_add_pcie_port(struct visconti_pcie *pcie,
>   				  struct platform_device *pdev)
>   {
>   	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>   
>   	pp->irq = platform_get_irq_byname(pdev, "intr");
>   	if (pp->irq < 0)


For pci-meson.c:
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Re: [PATCH RESEND v5 03/18] PCI: dwc: Disable outbound windows for controllers with iATU

[Bjorn Helgaas]

[+cc Jonathan for pcie-al.c, Kishon for pci-keystone.c]

On Fri, Jun 24, 2022 at 05:34:13PM +0300, Serge Semin wrote:
> In accordance with the dw_pcie_setup_rc() method semantics and judging by
> what the comment added in commit dd193929d91e ("PCI: designware: Explain
> why we don't program ATU for some platforms") states there are DWC
> PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's
> Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU
> enabled and use it's own address translation approach implemented. In
> these cases at the very least there is no point in touching the DW PCIe
> iATU CSRs. Moreover depending on the vendor-specific address translation
> implementation it might be even erroneous. So let's move the iATU windows
> disabling procedure to being under the corresponding conditional statement
> clause thus performing that procedure only if the iATU is expected to be
> available on the platform.

Added Jonathan and Kishon to make sure pcie-al.c and pci-keystone.c
(the only two drivers that override the default dw_child_pcie_ops)
won't be broken by skipping the outbound window disable.

> Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index bc9a7df130ef..d4326aae5a32 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -543,7 +543,6 @@ static struct pci_ops dw_pcie_ops = {
>  
>  void dw_pcie_setup_rc(struct pcie_port *pp)
>  {
> -	int i;
>  	u32 val, ctrl, num_ctrls;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
> @@ -594,19 +593,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  		PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
>  	dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
>  
> -	/* Ensure all outbound windows are disabled so there are multiple matches */
> -	for (i = 0; i < pci->num_ob_windows; i++)
> -		dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
> -
>  	/*
>  	 * If the platform provides its own child bus config accesses, it means
>  	 * the platform uses its own address translation component rather than
>  	 * ATU, so we should not program the ATU here.
>  	 */
>  	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> -		int atu_idx = 0;
> +		int i, atu_idx = 0;
>  		struct resource_entry *entry;
>  
> +		/*
> +		 * Ensure all outbound windows are disabled so there are
> +		 * multiple matches

I know you only moved this comment and didn't change the wording, but
do you know what it means?  What "multiple matches" is it talking
about, and why are they important?

I guess Rob previously moved it with 458ad06c4cdd ("PCI: dwc: Ensure
all outbound ATU windows are reset") [1], and it looks like maybe the
point is to *avoid* having an outbound transaction match multiple
windows?  So maybe this comment should say this?

  Disable all outbound windows to make sure a transaction can't match
  multiple windows.

[1] https://git.kernel.org/linus/458ad06c4cdd

> +		 */
> +		for (i = 0; i < pci->num_ob_windows; i++)
> +			dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
> +
>  		/* Get last memory resource entry */
>  		resource_list_for_each_entry(entry, &pp->bridge->windows) {
>  			if (resource_type(entry->res) != IORESOURCE_MEM)
> -- 
> 2.35.1
> 

Re: [PATCH RESEND v5 05/18] PCI: dwc: Deallocate EPC memory on EP init error

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:15PM +0300, Serge Semin wrote:
> If the dw_pcie_ep_init() method fails to perform any action after the EPC
> memory is initialized and the MSI memory region is allocated, the later
> parts won't be undone thus causing the memory leak.  Let's fix that by
> introducing the cleanup-on-error path in the dw_pcie_ep_init() method,
> which will be taken should any consequent erroneous situation happens.
> 
> Fixes: 2fd0c9d966cc ("PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v2:
> - This is a new patch create as a result of the discussion in:
>   Link: https://lore.kernel.org/linux-pci/20220324014836.19149-26-Sergey.Semin@baikalelectronics.ru
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c    | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 0eda8236c125..13c2e73f0eaf 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -780,8 +780,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  	ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
>  					     epc->mem->window.page_size);
>  	if (!ep->msi_mem) {
> +		ret = -ENOMEM;
>  		dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
> -		return -ENOMEM;
> +		goto err_exit_epc_mem;
>  	}
>  
>  	if (ep->ops->get_features) {
> @@ -790,6 +791,19 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  			return 0;
>  	}
>  
> -	return dw_pcie_ep_init_complete(ep);
> +	ret = dw_pcie_ep_init_complete(ep);
> +	if (ret)
> +		goto err_free_epc_mem;
> +
> +	return 0;
> +
> +err_free_epc_mem:
> +	pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> +			      epc->mem->window.page_size);
> +
> +err_exit_epc_mem:
> +	pci_epc_mem_exit(epc);
> +
> +	return ret;
>  }
>  EXPORT_SYMBOL_GPL(dw_pcie_ep_init);
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 06/18] PCI: dwc: Enable CDM-check independently from the num_lanes value

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:16PM +0300, Serge Semin wrote:
> Currently the embedded CDM IOs consistency check-engine is enabled only if
> the num_lanes field of dw_pcie structure is set to non-zero value. It's
> definitely wrong since the CDM checking has nothing to do with the PCIe
> lanes settings, while that feature will be left disabled for the platforms
> which expect it being enabled and prefer keeping the default lanes setup.
> Let's fix that by enabling the CDM-check feature before the num_lanes
> parameter is handled.
> 
> Fixes: 07f123def73e ("PCI: dwc: Add support to enable CDM register check")

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on v4 lap of the series.
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 347251bf87d0..5848cc520b52 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -740,6 +740,13 @@ void dw_pcie_setup(struct dw_pcie *pci)
>  	val |= PORT_LINK_DLL_LINK_EN;
>  	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
>  
> +	if (of_property_read_bool(np, "snps,enable-cdm-check")) {
> +		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
> +		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
> +		       PCIE_PL_CHK_REG_CHK_REG_START;
> +		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> +	}
> +
>  	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
>  	if (!pci->num_lanes) {
>  		dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> @@ -786,11 +793,4 @@ void dw_pcie_setup(struct dw_pcie *pci)
>  		break;
>  	}
>  	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> -
> -	if (of_property_read_bool(np, "snps,enable-cdm-check")) {
> -		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
> -		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
> -		       PCIE_PL_CHK_REG_CHK_REG_START;
> -		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
> -	}
>  }
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 11/18] PCI: dwc: Organize local variables usage

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:21PM +0300, Serge Semin wrote:
> There are several places in the common DW PCIe code with incoherent local
> variables usage: a variable is defined and initialized with a structure
> field, but the structure pointer is de-referenced to access that field
> anyway; the local variable is defined and initialized but either used just
> once or not used afterwards in the main part of the subsequent method.
> It's mainly concerns the pcie_port.dev field. Let's fix that in the
> relevant places.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------
>  drivers/pci/controller/dwc/pcie-designware.c      |  8 +++-----
>  2 files changed, 9 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 9a4922b714e5..54257874c154 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -296,7 +296,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  	struct resource *cfg_res;
>  	int ret;
>  
> -	raw_spin_lock_init(&pci->pp.lock);
> +	raw_spin_lock_init(&pp->lock);
>  
>  	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
>  	if (cfg_res) {
> @@ -388,15 +388,15 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  							    dw_chained_msi_isr,
>  							    pp);
>  
> -			ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> +			ret = dma_set_mask(dev, DMA_BIT_MASK(32));
>  			if (ret)
> -				dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
> +				dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
>  
> -			pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
> +			pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
>  						      sizeof(pp->msi_msg),
>  						      DMA_FROM_DEVICE,
>  						      DMA_ATTR_SKIP_CPU_SYNC);
> -			ret = dma_mapping_error(pci->dev, pp->msi_data);
> +			ret = dma_mapping_error(dev, pp->msi_data);
>  			if (ret) {
>  				dev_err(pci->dev, "Failed to map MSI data\n");
>  				pp->msi_data = 0;
> @@ -633,7 +633,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  		}
>  
>  		if (pci->num_ob_windows <= atu_idx)
> -			dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
> +			dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",
>  				 pci->num_ob_windows);
>  	}
>  
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index f9613835212b..ce01187947c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -677,8 +677,7 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
>  
>  void dw_pcie_iatu_detect(struct dw_pcie *pci)
>  {
> -	struct device *dev = pci->dev;
> -	struct platform_device *pdev = to_platform_device(dev);
> +	struct platform_device *pdev = to_platform_device(pci->dev);
>  
>  	pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
>  	if (pci->iatu_unroll_enabled) {
> @@ -687,7 +686,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
>  				platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
>  			if (res) {
>  				pci->atu_size = resource_size(res);
> -				pci->atu_base = devm_ioremap_resource(dev, res);
> +				pci->atu_base = devm_ioremap_resource(pci->dev, res);
>  			}
>  			if (!pci->atu_base || IS_ERR(pci->atu_base))
>  				pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
> @@ -711,9 +710,8 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
>  
>  void dw_pcie_setup(struct dw_pcie *pci)
>  {
> +	struct device_node *np = pci->dev->of_node;
>  	u32 val;
> -	struct device *dev = pci->dev;
> -	struct device_node *np = dev->of_node;
>  
>  	if (pci->link_gen > 0)
>  		dw_pcie_link_set_max_speed(pci, pci->link_gen);
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 12/18] PCI: dwc: Re-use local pointer to the resource data

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:22PM +0300, Serge Semin wrote:
> The dw_pcie_host_init() method has two instances of the resource structure
> pointers used in non-related places of the method. It's pointless to have
> two different local storages for them since the corresponding code is
> small and having resource specific names doesn't make it more readable.
> Let's convert these parts of the function to using just a common pointer
> to the resource structure instance. That shall make the code a bit nicer
> looking.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>  .../pci/controller/dwc/pcie-designware-host.c    | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 54257874c154..2f13eec4812d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -293,17 +293,17 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  	struct platform_device *pdev = to_platform_device(dev);
>  	struct resource_entry *win;
>  	struct pci_host_bridge *bridge;
> -	struct resource *cfg_res;
> +	struct resource *res;
>  	int ret;
>  
>  	raw_spin_lock_init(&pp->lock);
>  
> -	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> -	if (cfg_res) {
> -		pp->cfg0_size = resource_size(cfg_res);
> -		pp->cfg0_base = cfg_res->start;
> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> +	if (res) {
> +		pp->cfg0_size = resource_size(res);
> +		pp->cfg0_base = res->start;
>  
> -		pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res);
> +		pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
>  		if (IS_ERR(pp->va_cfg0_base))
>  			return PTR_ERR(pp->va_cfg0_base);
>  	} else {
> @@ -312,8 +312,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  	}
>  
>  	if (!pci->dbi_base) {
> -		struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> -		pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
> +		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> +		pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
>  		if (IS_ERR(pci->dbi_base))
>  			return PTR_ERR(pci->dbi_base);
>  	}
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 13/18] PCI: dwc: Add start_link/stop_link inliners

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:23PM +0300, Serge Semin wrote:
> There are several places in the generic DW PCIe code where the
> platform-specific PCIe link start/stop methods are called after making
> sure the ops handler and the callbacks are specified. Instead of repeating
> the same pattern over and over let's define the static-inline methods in
> the DW PCIe header file and use them in the relevant parts of the driver.
> 
> Note returning a negative error from the EP link start procedure if the
> start_link pointer isn't specified doesn't really make much sense since
> it's perfectly normal to have such a platform. Moreover even
> pci_epc_start() doesn't fail if no epc->ops->start callback is spotted. As
> a side-effect of this modification we can set the generic DW PCIe and
> Layerscape EP platform drivers free from the empty start_link callbacks
> and as such entirely dummy dw_pcie_ops instances.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>  drivers/pci/controller/dwc/pci-layerscape-ep.c    | 12 ------------
>  drivers/pci/controller/dwc/pcie-designware-ep.c   |  8 ++------
>  drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++------
>  drivers/pci/controller/dwc/pcie-designware-plat.c | 10 ----------
>  drivers/pci/controller/dwc/pcie-designware.h      | 14 ++++++++++++++
>  5 files changed, 20 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 39f4664bd84c..ad99707b3b99 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -32,15 +32,6 @@ struct ls_pcie_ep {
>  	const struct ls_pcie_ep_drvdata *drvdata;
>  };
>  
> -static int ls_pcie_establish_link(struct dw_pcie *pci)
> -{
> -	return 0;
> -}
> -
> -static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
> -	.start_link = ls_pcie_establish_link,
> -};
> -
>  static const struct pci_epc_features*
>  ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
>  {
> @@ -106,19 +97,16 @@ static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
>  
>  static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
>  	.ops = &ls_pcie_ep_ops,
> -	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
>  };
>  
>  static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
>  	.func_offset = 0x20000,
>  	.ops = &ls_pcie_ep_ops,
> -	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
>  };
>  
>  static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = {
>  	.func_offset = 0x8000,
>  	.ops = &ls_pcie_ep_ops,
> -	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
>  };
>  
>  static const struct of_device_id ls_pcie_ep_of_match[] = {
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7ad349c32082..15b8059544e3 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -435,8 +435,7 @@ static void dw_pcie_ep_stop(struct pci_epc *epc)
>  	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>  
> -	if (pci->ops && pci->ops->stop_link)
> -		pci->ops->stop_link(pci);
> +	dw_pcie_stop_link(pci);
>  }
>  
>  static int dw_pcie_ep_start(struct pci_epc *epc)
> @@ -444,10 +443,7 @@ static int dw_pcie_ep_start(struct pci_epc *epc)
>  	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>  
> -	if (!pci->ops || !pci->ops->start_link)
> -		return -EINVAL;
> -
> -	return pci->ops->start_link(pci);
> +	return dw_pcie_start_link(pci);
>  }
>  
>  static const struct pci_epc_features*
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 2f13eec4812d..c49a3bde7a2a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -409,8 +409,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  
>  	dw_pcie_setup_rc(pp);
>  
> -	if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
> -		ret = pci->ops->start_link(pci);
> +	if (!dw_pcie_link_up(pci)) {
> +		ret = dw_pcie_start_link(pci);
>  		if (ret)
>  			goto err_free_msi;
>  	}
> @@ -427,8 +427,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  	return 0;
>  
>  err_stop_link:
> -	if (pci->ops && pci->ops->stop_link)
> -		pci->ops->stop_link(pci);
> +	dw_pcie_stop_link(pci);
>  
>  err_free_msi:
>  	if (pp->has_msi_ctrl)
> @@ -444,8 +443,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp)
>  	pci_stop_root_bus(pp->bridge->bus);
>  	pci_remove_root_bus(pp->bridge->bus);
>  
> -	if (pci->ops && pci->ops->stop_link)
> -		pci->ops->stop_link(pci);
> +	dw_pcie_stop_link(pci);
>  
>  	if (pp->has_msi_ctrl)
>  		dw_pcie_free_msi(pp);
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index 0c5de87d3cc6..abf1afac6064 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -36,15 +36,6 @@ static const struct of_device_id dw_plat_pcie_of_match[];
>  static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
>  };
>  
> -static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
> -{
> -	return 0;
> -}
> -
> -static const struct dw_pcie_ops dw_pcie_ops = {
> -	.start_link = dw_plat_pcie_establish_link,
> -};
> -
>  static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -140,7 +131,6 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	pci->dev = dev;
> -	pci->ops = &dw_pcie_ops;
>  
>  	dw_plat_pcie->pci = pci;
>  	dw_plat_pcie->mode = mode;
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 7d6e9b7576be..8ba239292634 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -365,6 +365,20 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
>  	dw_pcie_writel_dbi(pci, reg, val);
>  }
>  
> +static inline int dw_pcie_start_link(struct dw_pcie *pci)
> +{
> +	if (pci->ops && pci->ops->start_link)
> +		return pci->ops->start_link(pci);
> +
> +	return 0;
> +}
> +
> +static inline void dw_pcie_stop_link(struct dw_pcie *pci)
> +{
> +	if (pci->ops && pci->ops->stop_link)
> +		pci->ops->stop_link(pci);
> +}
> +
>  #ifdef CONFIG_PCIE_DW_HOST
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 14/18] PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:24PM +0300, Serge Semin wrote:
> That flag is set if there is an outbound iATU window used for both PCIe
> peripheral config-space accesses and IO ports transfers. Since the flag
> semantic is purely Root Port specific, it's unused in neither the DW PCIe
> common code nor in the DW PCIe Endpoint driver, we can freely move it to
> the DW PCIe Root Port descriptor. Thus the pcie_port structure will be
> more coherent.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 6 +++---
>  drivers/pci/controller/dwc/pcie-designware.h      | 2 +-
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index c49a3bde7a2a..7ff2b7555b91 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -492,7 +492,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
>  
>  	ret = pci_generic_config_read(bus, devfn, where, size, val);
>  
> -	if (!ret && pci->io_cfg_atu_shared)
> +	if (!ret && pp->cfg0_io_shared)
>  		dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
>  					  pp->io_bus_addr, pp->io_size);
>  
> @@ -508,7 +508,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
>  
>  	ret = pci_generic_config_write(bus, devfn, where, size, val);
>  
> -	if (!ret && pci->io_cfg_atu_shared)
> +	if (!ret && pp->cfg0_io_shared)
>  		dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
>  					  pp->io_bus_addr, pp->io_size);
>  
> @@ -627,7 +627,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  							  PCIE_ATU_TYPE_IO, pp->io_base,
>  							  pp->io_bus_addr, pp->io_size);
>  			else
> -				pci->io_cfg_atu_shared = true;
> +				pp->cfg0_io_shared = true;
>  		}
>  
>  		if (pci->num_ob_windows <= atu_idx)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 8ba239292634..13bffa3eaed6 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -179,6 +179,7 @@ struct dw_pcie_host_ops {
>  
>  struct pcie_port {
>  	bool			has_msi_ctrl:1;
> +	bool			cfg0_io_shared:1;
>  	u64			cfg0_base;
>  	void __iomem		*va_cfg0_base;
>  	u32			cfg0_size;
> @@ -274,7 +275,6 @@ struct dw_pcie {
>  	int			link_gen;
>  	u8			n_fts[2];
>  	bool			iatu_unroll_enabled: 1;
> -	bool			io_cfg_atu_shared: 1;
>  };
>  
>  #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 15/18] PCI: dwc: Add dw_ prefix to the pcie_port structure name

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:25PM +0300, Serge Semin wrote:
> All of the DW PCIe core driver entities have names with the dw_ prefix in
> order to easily distinguish local and common PCIe name spaces. All except
> the pcie_port structure which contains the DW PCIe Root Port descriptor.
> For historical reason the structure has retained the original name since
> commit 340cba6092c2 ("pci: Add PCIe driver for Samsung Exynos") when
> the DW PCIe IP-core support was added to the kernel. Let's finally fix
> that by adding the dw_ prefix to the structure name and by adding the _rp
> suffix to be similar to the EP counterpart. Thus the name will be coherent
> with the common driver naming policy. It shall make the driver code more
> readable eliminating visual confusion between the local and generic PCI
> name spaces.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>  drivers/pci/controller/dwc/pci-dra7xx.c       | 12 +++----
>  drivers/pci/controller/dwc/pci-exynos.c       |  6 ++--
>  drivers/pci/controller/dwc/pci-imx6.c         |  6 ++--
>  drivers/pci/controller/dwc/pci-keystone.c     | 20 +++++------
>  drivers/pci/controller/dwc/pci-layerscape.c   |  2 +-
>  drivers/pci/controller/dwc/pci-meson.c        |  2 +-
>  drivers/pci/controller/dwc/pcie-al.c          |  6 ++--
>  drivers/pci/controller/dwc/pcie-armada8k.c    |  4 +--
>  drivers/pci/controller/dwc/pcie-artpec6.c     |  4 +--
>  .../pci/controller/dwc/pcie-designware-host.c | 36 +++++++++----------
>  .../pci/controller/dwc/pcie-designware-plat.c |  2 +-
>  drivers/pci/controller/dwc/pcie-designware.h  | 30 ++++++++--------
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c |  4 +--
>  drivers/pci/controller/dwc/pcie-fu740.c       |  2 +-
>  drivers/pci/controller/dwc/pcie-histb.c       | 10 +++---
>  drivers/pci/controller/dwc/pcie-intel-gw.c    |  6 ++--
>  drivers/pci/controller/dwc/pcie-keembay.c     |  4 +--
>  drivers/pci/controller/dwc/pcie-kirin.c       |  2 +-
>  drivers/pci/controller/dwc/pcie-qcom.c        |  4 +--
>  drivers/pci/controller/dwc/pcie-spear13xx.c   |  6 ++--
>  drivers/pci/controller/dwc/pcie-tegra194.c    | 22 ++++++------
>  drivers/pci/controller/dwc/pcie-uniphier.c    | 10 +++---
>  drivers/pci/controller/dwc/pcie-visconti.c    |  6 ++--
>  23 files changed, 103 insertions(+), 103 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index dfcdeb432dc8..a174b680b2a7 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -178,7 +178,7 @@ static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
>  	dra7xx_pcie_enable_msi_interrupts(dra7xx);
>  }
>  
> -static int dra7xx_pcie_host_init(struct pcie_port *pp)
> +static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> @@ -202,7 +202,7 @@ static const struct irq_domain_ops intx_domain_ops = {
>  	.xlate = pci_irqd_intx_xlate,
>  };
>  
> -static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
> +static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	unsigned long val;
> @@ -224,7 +224,7 @@ static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
>  	return 1;
>  }
>  
> -static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
> +static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	int ret, i, count, num_ctrls;
> @@ -255,8 +255,8 @@ static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
>  {
>  	struct irq_chip *chip = irq_desc_get_chip(desc);
>  	struct dra7xx_pcie *dra7xx;
> +	struct dw_pcie_rp *pp;
>  	struct dw_pcie *pci;
> -	struct pcie_port *pp;
>  	unsigned long reg;
>  	u32 bit;
>  
> @@ -344,7 +344,7 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
>  	return IRQ_HANDLED;
>  }
>  
> -static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
> +static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct device *dev = pci->dev;
> @@ -475,7 +475,7 @@ static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
>  {
>  	int ret;
>  	struct dw_pcie *pci = dra7xx->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = pci->dev;
>  
>  	pp->irq = platform_get_irq(pdev, 1);
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index 467c8d1cd7e4..2044d191fba6 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -249,7 +249,7 @@ static int exynos_pcie_link_up(struct dw_pcie *pci)
>  	return (val & PCIE_ELBI_XMLH_LINKUP);
>  }
>  
> -static int exynos_pcie_host_init(struct pcie_port *pp)
> +static int exynos_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct exynos_pcie *ep = to_exynos_pcie(pci);
> @@ -276,7 +276,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep,
>  				       struct platform_device *pdev)
>  {
>  	struct dw_pcie *pci = &ep->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = &pdev->dev;
>  	int ret;
>  
> @@ -406,7 +406,7 @@ static int __maybe_unused exynos_pcie_resume_noirq(struct device *dev)
>  {
>  	struct exynos_pcie *ep = dev_get_drvdata(dev);
>  	struct dw_pcie *pci = &ep->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	int ret;
>  
>  	ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies);
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 7a285fb0f619..5ea01ed4674d 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -863,7 +863,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
>  	return ret;
>  }
>  
> -static int imx6_pcie_host_init(struct pcie_port *pp)
> +static int imx6_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> @@ -992,7 +992,7 @@ static int imx6_pcie_resume_noirq(struct device *dev)
>  {
>  	int ret;
>  	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> -	struct pcie_port *pp = &imx6_pcie->pci->pp;
> +	struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
>  
>  	if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
>  		return 0;
> @@ -1291,7 +1291,7 @@ static struct platform_driver imx6_pcie_driver = {
>  static void imx6_pcie_quirk(struct pci_dev *dev)
>  {
>  	struct pci_bus *bus = dev->bus;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  
>  	/* Bus parent is the PCI bridge, its parent is this platform driver */
>  	if (!bus->dev.parent || !bus->dev.parent->parent)
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index d10e5fd0f83c..c3d88aa27dd4 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -147,7 +147,7 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
>  
>  static void ks_pcie_msi_irq_ack(struct irq_data *data)
>  {
> -	struct pcie_port *pp  = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(data);
>  	struct keystone_pcie *ks_pcie;
>  	u32 irq = data->hwirq;
>  	struct dw_pcie *pci;
> @@ -167,7 +167,7 @@ static void ks_pcie_msi_irq_ack(struct irq_data *data)
>  
>  static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
>  	struct keystone_pcie *ks_pcie;
>  	struct dw_pcie *pci;
>  	u64 msi_target;
> @@ -192,7 +192,7 @@ static int ks_pcie_msi_set_affinity(struct irq_data *irq_data,
>  
>  static void ks_pcie_msi_mask(struct irq_data *data)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
>  	struct keystone_pcie *ks_pcie;
>  	u32 irq = data->hwirq;
>  	struct dw_pcie *pci;
> @@ -216,7 +216,7 @@ static void ks_pcie_msi_mask(struct irq_data *data)
>  
>  static void ks_pcie_msi_unmask(struct irq_data *data)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(data);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data);
>  	struct keystone_pcie *ks_pcie;
>  	u32 irq = data->hwirq;
>  	struct dw_pcie *pci;
> @@ -247,7 +247,7 @@ static struct irq_chip ks_pcie_msi_irq_chip = {
>  	.irq_unmask = ks_pcie_msi_unmask,
>  };
>  
> -static int ks_pcie_msi_host_init(struct pcie_port *pp)
> +static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp)
>  {
>  	pp->msi_irq_chip = &ks_pcie_msi_irq_chip;
>  	return dw_pcie_allocate_domains(pp);
> @@ -390,7 +390,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>  	u32 val;
>  	u32 num_viewport = ks_pcie->num_viewport;
>  	struct dw_pcie *pci = ks_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	u64 start, end;
>  	struct resource *mem;
>  	int i;
> @@ -428,7 +428,7 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>  static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
>  					   unsigned int devfn, int where)
>  {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>  	u32 reg;
> @@ -456,7 +456,7 @@ static struct pci_ops ks_child_pcie_ops = {
>   */
>  static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
>  {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>  
> @@ -574,7 +574,7 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
>  	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
>  	u32 offset = irq - ks_pcie->msi_host_irq;
>  	struct dw_pcie *pci = ks_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = pci->dev;
>  	struct irq_chip *chip = irq_desc_get_chip(desc);
>  	u32 vector, reg, pos;
> @@ -799,7 +799,7 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
>  	return 0;
>  }
>  
> -static int __init ks_pcie_host_init(struct pcie_port *pp)
> +static int __init ks_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
> index 6a4f0619bb1c..879b8692f96a 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape.c
> @@ -74,7 +74,7 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
>  	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
>  }
>  
> -static int ls_pcie_host_init(struct pcie_port *pp)
> +static int ls_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct ls_pcie *pcie = to_ls_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
> index f44bf347904a..c1527693bed9 100644
> --- a/drivers/pci/controller/dwc/pci-meson.c
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -370,7 +370,7 @@ static int meson_pcie_link_up(struct dw_pcie *pci)
>  	return 0;
>  }
>  
> -static int meson_pcie_host_init(struct pcie_port *pp)
> +static int meson_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct meson_pcie *mp = to_meson_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c
> index e8afa50129a8..b8cb77c9c4bd 100644
> --- a/drivers/pci/controller/dwc/pcie-al.c
> +++ b/drivers/pci/controller/dwc/pcie-al.c
> @@ -217,7 +217,7 @@ static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
>  static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus,
>  					       unsigned int devfn, int where)
>  {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
>  	unsigned int busnr = bus->number;
>  	struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
> @@ -245,7 +245,7 @@ static struct pci_ops al_child_pci_ops = {
>  static void al_pcie_config_prepare(struct al_pcie *pcie)
>  {
>  	struct al_pcie_target_bus_cfg *target_bus_cfg;
> -	struct pcie_port *pp = &pcie->pci->pp;
> +	struct dw_pcie_rp *pp = &pcie->pci->pp;
>  	unsigned int ecam_bus_mask;
>  	u32 cfg_control_offset;
>  	u8 subordinate_bus;
> @@ -289,7 +289,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie)
>  	al_pcie_controller_writel(pcie, cfg_control_offset, reg);
>  }
>  
> -static int al_pcie_host_init(struct pcie_port *pp)
> +static int al_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct al_pcie *pcie = to_al_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
> index 4e2552dcf982..8b113d3f3095 100644
> --- a/drivers/pci/controller/dwc/pcie-armada8k.c
> +++ b/drivers/pci/controller/dwc/pcie-armada8k.c
> @@ -166,7 +166,7 @@ static int armada8k_pcie_start_link(struct dw_pcie *pci)
>  	return 0;
>  }
>  
> -static int armada8k_pcie_host_init(struct pcie_port *pp)
> +static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	u32 reg;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -233,7 +233,7 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
>  				  struct platform_device *pdev)
>  {
>  	struct dw_pcie *pci = pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = &pdev->dev;
>  	int ret;
>  
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index 2f15441770e1..98102079e26d 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -97,7 +97,7 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
>  static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
>  {
>  	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct dw_pcie_ep *ep = &pci->ep;
>  
>  	switch (artpec6_pcie->mode) {
> @@ -315,7 +315,7 @@ static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
>  	usleep_range(100, 200);
>  }
>  
> -static int artpec6_pcie_host_init(struct pcie_port *pp)
> +static int artpec6_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 7ff2b7555b91..95256434913f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -53,7 +53,7 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
>  };
>  
>  /* MSI int handler */
> -irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> +irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
>  {
>  	int i, pos;
>  	unsigned long val;
> @@ -88,7 +88,7 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>  static void dw_chained_msi_isr(struct irq_desc *desc)
>  {
>  	struct irq_chip *chip = irq_desc_get_chip(desc);
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  
>  	chained_irq_enter(chip, desc);
>  
> @@ -100,7 +100,7 @@ static void dw_chained_msi_isr(struct irq_desc *desc)
>  
>  static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	u64 msi_target;
>  
> @@ -123,7 +123,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d,
>  
>  static void dw_pci_bottom_mask(struct irq_data *d)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	unsigned int res, bit, ctrl;
>  	unsigned long flags;
> @@ -142,7 +142,7 @@ static void dw_pci_bottom_mask(struct irq_data *d)
>  
>  static void dw_pci_bottom_unmask(struct irq_data *d)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	unsigned int res, bit, ctrl;
>  	unsigned long flags;
> @@ -161,7 +161,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d)
>  
>  static void dw_pci_bottom_ack(struct irq_data *d)
>  {
> -	struct pcie_port *pp  = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(d);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	unsigned int res, bit, ctrl;
>  
> @@ -185,7 +185,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
>  				    unsigned int virq, unsigned int nr_irqs,
>  				    void *args)
>  {
> -	struct pcie_port *pp = domain->host_data;
> +	struct dw_pcie_rp *pp = domain->host_data;
>  	unsigned long flags;
>  	u32 i;
>  	int bit;
> @@ -213,7 +213,7 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain,
>  				    unsigned int virq, unsigned int nr_irqs)
>  {
>  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> -	struct pcie_port *pp = domain->host_data;
> +	struct dw_pcie_rp *pp = domain->host_data;
>  	unsigned long flags;
>  
>  	raw_spin_lock_irqsave(&pp->lock, flags);
> @@ -229,7 +229,7 @@ static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
>  	.free	= dw_pcie_irq_domain_free,
>  };
>  
> -int dw_pcie_allocate_domains(struct pcie_port *pp)
> +int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
> @@ -255,7 +255,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
>  	return 0;
>  }
>  
> -static void dw_pcie_free_msi(struct pcie_port *pp)
> +static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
>  {
>  	if (pp->msi_irq)
>  		irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
> @@ -272,7 +272,7 @@ static void dw_pcie_free_msi(struct pcie_port *pp)
>  	}
>  }
>  
> -static void dw_pcie_msi_init(struct pcie_port *pp)
> +static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	u64 msi_target = (u64)pp->msi_data;
> @@ -285,7 +285,7 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
>  	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
>  }
>  
> -int dw_pcie_host_init(struct pcie_port *pp)
> +int dw_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct device *dev = pci->dev;
> @@ -436,7 +436,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  }
>  EXPORT_SYMBOL_GPL(dw_pcie_host_init);
>  
> -void dw_pcie_host_deinit(struct pcie_port *pp)
> +void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
> @@ -455,7 +455,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
>  {
>  	int type;
>  	u32 busdev;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
>  	/*
> @@ -487,7 +487,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
>  				 int where, int size, u32 *val)
>  {
>  	int ret;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
>  	ret = pci_generic_config_read(bus, devfn, where, size, val);
> @@ -503,7 +503,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
>  				 int where, int size, u32 val)
>  {
>  	int ret;
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
>  	ret = pci_generic_config_write(bus, devfn, where, size, val);
> @@ -523,7 +523,7 @@ static struct pci_ops dw_child_pcie_ops = {
>  
>  void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
>  {
> -	struct pcie_port *pp = bus->sysdata;
> +	struct dw_pcie_rp *pp = bus->sysdata;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
>  	if (PCI_SLOT(devfn) > 0)
> @@ -539,7 +539,7 @@ static struct pci_ops dw_pcie_ops = {
>  	.write = pci_generic_config_write,
>  };
>  
> -void dw_pcie_setup_rc(struct pcie_port *pp)
> +void dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>  {
>  	u32 val, ctrl, num_ctrls;
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index abf1afac6064..97de6ad7f9db 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -87,7 +87,7 @@ static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
>  				 struct platform_device *pdev)
>  {
>  	struct dw_pcie *pci = dw_plat_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = &pdev->dev;
>  	int ret;
>  
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 13bffa3eaed6..32df3ebccf19 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -155,8 +155,8 @@
>  #define MAX_IATU_IN			256
>  #define MAX_IATU_OUT			256
>  
> -struct pcie_port;
>  struct dw_pcie;
> +struct dw_pcie_rp;
>  struct dw_pcie_ep;
>  
>  enum dw_pcie_region_type {
> @@ -173,11 +173,11 @@ enum dw_pcie_device_mode {
>  };
>  
>  struct dw_pcie_host_ops {
> -	int (*host_init)(struct pcie_port *pp);
> -	int (*msi_host_init)(struct pcie_port *pp);
> +	int (*host_init)(struct dw_pcie_rp *pp);
> +	int (*msi_host_init)(struct dw_pcie_rp *pp);
>  };
>  
> -struct pcie_port {
> +struct dw_pcie_rp {
>  	bool			has_msi_ctrl:1;
>  	bool			cfg0_io_shared:1;
>  	u64			cfg0_base;
> @@ -267,7 +267,7 @@ struct dw_pcie {
>  	size_t			atu_size;
>  	u32			num_ib_windows;
>  	u32			num_ob_windows;
> -	struct pcie_port	pp;
> +	struct dw_pcie_rp	pp;
>  	struct dw_pcie_ep	ep;
>  	const struct dw_pcie_ops *ops;
>  	unsigned int		version;
> @@ -380,33 +380,33 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci)
>  }
>  
>  #ifdef CONFIG_PCIE_DW_HOST
> -irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
> -void dw_pcie_setup_rc(struct pcie_port *pp);
> -int dw_pcie_host_init(struct pcie_port *pp);
> -void dw_pcie_host_deinit(struct pcie_port *pp);
> -int dw_pcie_allocate_domains(struct pcie_port *pp);
> +irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
> +void dw_pcie_setup_rc(struct dw_pcie_rp *pp);
> +int dw_pcie_host_init(struct dw_pcie_rp *pp);
> +void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
> +int dw_pcie_allocate_domains(struct dw_pcie_rp *pp);
>  void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
>  				       int where);
>  #else
> -static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> +static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
>  {
>  	return IRQ_NONE;
>  }
>  
> -static inline void dw_pcie_setup_rc(struct pcie_port *pp)
> +static inline void dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>  {
>  }
>  
> -static inline int dw_pcie_host_init(struct pcie_port *pp)
> +static inline int dw_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	return 0;
>  }
>  
> -static inline void dw_pcie_host_deinit(struct pcie_port *pp)
> +static inline void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
>  {
>  }
>  
> -static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
> +static inline int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
>  {
>  	return 0;
>  }
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 8c5bb9d7cc36..c1e7653e508e 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -186,7 +186,7 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
>  	return 0;
>  }
>  
> -static int rockchip_pcie_host_init(struct pcie_port *pp)
> +static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> @@ -288,7 +288,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	struct rockchip_pcie *rockchip;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  	int ret;
>  
>  	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
> diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c
> index 02cc70d8cc06..da059f1c9e92 100644
> --- a/drivers/pci/controller/dwc/pcie-fu740.c
> +++ b/drivers/pci/controller/dwc/pcie-fu740.c
> @@ -236,7 +236,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci)
>  	return ret;
>  }
>  
> -static int fu740_pcie_host_init(struct pcie_port *pp)
> +static int fu740_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct fu740_pcie *afp = to_fu740_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
> index 410555dccb6d..e2b80f10030d 100644
> --- a/drivers/pci/controller/dwc/pcie-histb.c
> +++ b/drivers/pci/controller/dwc/pcie-histb.c
> @@ -74,7 +74,7 @@ static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val)
>  	writel(val, histb_pcie->ctrl + reg);
>  }
>  
> -static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
> +static void histb_pcie_dbi_w_mode(struct dw_pcie_rp *pp, bool enable)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -88,7 +88,7 @@ static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
>  	histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val);
>  }
>  
> -static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable)
> +static void histb_pcie_dbi_r_mode(struct dw_pcie_rp *pp, bool enable)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -180,7 +180,7 @@ static int histb_pcie_start_link(struct dw_pcie *pci)
>  	return 0;
>  }
>  
> -static int histb_pcie_host_init(struct pcie_port *pp)
> +static int histb_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -219,7 +219,7 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie)
>  		regulator_disable(hipcie->vpcie);
>  }
>  
> -static int histb_pcie_host_enable(struct pcie_port *pp)
> +static int histb_pcie_host_enable(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct histb_pcie *hipcie = to_histb_pcie(pci);
> @@ -297,7 +297,7 @@ static int histb_pcie_probe(struct platform_device *pdev)
>  {
>  	struct histb_pcie *hipcie;
>  	struct dw_pcie *pci;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  	struct device_node *np = pdev->dev.of_node;
>  	struct device *dev = &pdev->dev;
>  	enum of_gpio_flags of_flags;
> diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
> index 5ba144924ff8..07bc54886d71 100644
> --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
> +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
> @@ -343,7 +343,7 @@ static void __intel_pcie_remove(struct intel_pcie *pcie)
>  static int intel_pcie_remove(struct platform_device *pdev)
>  {
>  	struct intel_pcie *pcie = platform_get_drvdata(pdev);
> -	struct pcie_port *pp = &pcie->pci.pp;
> +	struct dw_pcie_rp *pp = &pcie->pci.pp;
>  
>  	dw_pcie_host_deinit(pp);
>  	__intel_pcie_remove(pcie);
> @@ -373,7 +373,7 @@ static int __maybe_unused intel_pcie_resume_noirq(struct device *dev)
>  	return intel_pcie_host_setup(pcie);
>  }
>  
> -static int intel_pcie_rc_init(struct pcie_port *pp)
> +static int intel_pcie_rc_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct intel_pcie *pcie = dev_get_drvdata(pci->dev);
> @@ -403,7 +403,7 @@ static int intel_pcie_probe(struct platform_device *pdev)
>  	const struct intel_pcie_soc *data;
>  	struct device *dev = &pdev->dev;
>  	struct intel_pcie *pcie;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  	struct dw_pcie *pci;
>  	int ret;
>  
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 1ac29a6eef22..58f3caf75cff 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -231,7 +231,7 @@ static void keembay_pcie_msi_irq_handler(struct irq_desc *desc)
>  	struct keembay_pcie *pcie = irq_desc_get_handler_data(desc);
>  	struct irq_chip *chip = irq_desc_get_chip(desc);
>  	u32 val, mask, status;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  
>  	/*
>  	 * Keem Bay PCIe Controller provides an additional IP logic on top of
> @@ -332,7 +332,7 @@ static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie,
>  				      struct platform_device *pdev)
>  {
>  	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = &pdev->dev;
>  	u32 val;
>  	int ret;
> diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
> index a52cad269f85..7f67aad71df4 100644
> --- a/drivers/pci/controller/dwc/pcie-kirin.c
> +++ b/drivers/pci/controller/dwc/pcie-kirin.c
> @@ -620,7 +620,7 @@ static int kirin_pcie_start_link(struct dw_pcie *pci)
>  	return 0;
>  }
>  
> -static int kirin_pcie_host_init(struct pcie_port *pp)
> +static int kirin_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	pp->bridge->ops = &kirin_pci_ops;
>  
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 2ea13750b492..a9b2322624d5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1381,7 +1381,7 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie)
>  	return 0;
>  }
>  
> -static int qcom_pcie_host_init(struct pcie_port *pp)
> +static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct qcom_pcie *pcie = to_qcom_pcie(pci);
> @@ -1564,7 +1564,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
>  static int qcom_pcie_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  	struct dw_pcie *pci;
>  	struct qcom_pcie *pcie;
>  	const struct qcom_pcie_cfg *pcie_cfg;
> diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
> index 1569e82b5568..7fd698da144e 100644
> --- a/drivers/pci/controller/dwc/pcie-spear13xx.c
> +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
> @@ -85,7 +85,7 @@ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
>  	struct spear13xx_pcie *spear13xx_pcie = arg;
>  	struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
>  	struct dw_pcie *pci = spear13xx_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	unsigned int status;
>  
>  	status = readl(&app_reg->int_sts);
> @@ -121,7 +121,7 @@ static int spear13xx_pcie_link_up(struct dw_pcie *pci)
>  	return 0;
>  }
>  
> -static int spear13xx_pcie_host_init(struct pcie_port *pp)
> +static int spear13xx_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
> @@ -155,7 +155,7 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
>  				   struct platform_device *pdev)
>  {
>  	struct dw_pcie *pci = spear13xx_pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	struct device *dev = &pdev->dev;
>  	int ret;
>  
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index cc2678490162..65135f5c4a4a 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -311,7 +311,7 @@ struct tegra_pcie_soc {
>  	enum dw_pcie_device_mode mode;
>  };
>  
> -static void apply_bad_link_workaround(struct pcie_port *pp)
> +static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -349,7 +349,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
>  {
>  	struct tegra194_pcie *pcie = arg;
>  	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	u32 val, tmp;
>  	u16 val_w;
>  
> @@ -698,7 +698,7 @@ static inline void init_host_aspm(struct tegra194_pcie *pcie) { return; }
>  static inline void init_debugfs(struct tegra194_pcie *pcie) { return; }
>  #endif
>  
> -static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_system_interrupts(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -736,7 +736,7 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
>  			   val_w);
>  }
>  
> -static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -757,7 +757,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
>  }
>  
> -static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_msi_interrupts(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -770,7 +770,7 @@ static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
>  	appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>  }
>  
> -static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
> +static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -851,7 +851,7 @@ static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)
>  	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>  }
>  
> -static int tegra194_pcie_host_init(struct pcie_port *pp)
> +static int tegra194_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> @@ -916,7 +916,7 @@ static int tegra194_pcie_start_link(struct dw_pcie *pci)
>  {
>  	u32 val, offset, speed, tmp;
>  	struct tegra194_pcie *pcie = to_tegra_pcie(pci);
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	bool retry = true;
>  
>  	if (pcie->mode == DW_PCIE_EP_TYPE) {
> @@ -1212,7 +1212,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie,
>  
>  static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)
>  {
> -	struct pcie_port *pp = &pcie->pci.pp;
> +	struct dw_pcie_rp *pp = &pcie->pci.pp;
>  	struct pci_bus *child, *root_bus = NULL;
>  	struct pci_dev *pdev;
>  
> @@ -1443,7 +1443,7 @@ static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie)
>  static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
>  {
>  	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  	int ret;
>  
>  	ret = tegra_pcie_config_controller(pcie, false);
> @@ -1961,7 +1961,7 @@ static int tegra194_pcie_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct resource *atu_dma_res;
>  	struct tegra194_pcie *pcie;
> -	struct pcie_port *pp;
> +	struct dw_pcie_rp *pp;
>  	struct dw_pcie *pci;
>  	struct phy **phys;
>  	char *name;
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
> index b45ac3754242..48c3eba817b4 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
> @@ -171,7 +171,7 @@ static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie)
>  
>  static void uniphier_pcie_irq_mask(struct irq_data *d)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
>  	unsigned long flags;
> @@ -188,7 +188,7 @@ static void uniphier_pcie_irq_mask(struct irq_data *d)
>  
>  static void uniphier_pcie_irq_unmask(struct irq_data *d)
>  {
> -	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
> +	struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
>  	unsigned long flags;
> @@ -225,7 +225,7 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = {
>  
>  static void uniphier_pcie_irq_handler(struct irq_desc *desc)
>  {
> -	struct pcie_port *pp = irq_desc_get_handler_data(desc);
> +	struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
>  	struct irq_chip *chip = irq_desc_get_chip(desc);
> @@ -258,7 +258,7 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)
>  	chained_irq_exit(chip, desc);
>  }
>  
> -static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
> +static int uniphier_pcie_config_legacy_irq(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
> @@ -295,7 +295,7 @@ static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
>  	return ret;
>  }
>  
> -static int uniphier_pcie_host_init(struct pcie_port *pp)
> +static int uniphier_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
> index 50f80f07e4db..71026fefa366 100644
> --- a/drivers/pci/controller/dwc/pcie-visconti.c
> +++ b/drivers/pci/controller/dwc/pcie-visconti.c
> @@ -178,7 +178,7 @@ static void visconti_pcie_stop_link(struct dw_pcie *pci)
>   */
>  static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
>  {
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  
>  	return cpu_addr & ~pp->io_base;
>  }
> @@ -190,7 +190,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
>  	.stop_link = visconti_pcie_stop_link,
>  };
>  
> -static int visconti_pcie_host_init(struct pcie_port *pp)
> +static int visconti_pcie_host_init(struct dw_pcie_rp *pp)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
> @@ -278,7 +278,7 @@ static int visconti_add_pcie_port(struct visconti_pcie *pcie,
>  				  struct platform_device *pdev)
>  {
>  	struct dw_pcie *pci = &pcie->pci;
> -	struct pcie_port *pp = &pci->pp;
> +	struct dw_pcie_rp *pp = &pci->pp;
>  
>  	pp->irq = platform_get_irq_byname(pdev, "intr");
>  	if (pp->irq < 0)
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[Manivannan Sadhasivam]

On Fri, Jun 24, 2022 at 05:34:10PM +0300, Serge Semin wrote:
> This patchset is a first one in the series created in the framework of
> my Baikal-T1 PCIe/eDMA-related work:
> 
> [1: In-progress v5] PCI: dwc: Various fixes and cleanups
> Link: ---you are looking at it---
> [2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support
> Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru/
> [3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support
> Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru/
> [4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support
> Link: https://lore.kernel.org/linux-pci/20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru/
> 
> Note it is very recommended to merge the patchsets in the same order as
> they are placed in the list above in order to prevent possible merge
> conflicts. Nothing prevents them from being reviewed synchronously though.
> Any tests are very welcome!
> 
> As it can be easily inferred from the patchset title, this series is about
> the DW PCIe Root Port/Endpoint driver fixes and the code cleanups, where
> fixes come before the cleanup patches. The patchset starts with adding the
> stop_link() platform-specific method invocation in case of the PCIe host
> probe procedure errors. It has been missing in the cleanup-on-error path
> of the DW PCIe Host initialization method. After that the unrolled CSRs
> layout is added to the iATU disable procedure. In third the disable iATU
> procedure is fixed to be called only for the internal ATU as being
> specific for the internal ATU implementation. Then the outbound iATU
> extended region setup procedure is fixed to have the INCREASE_REGION_SIZE
> flag set based on the limit-address - not the region size one. The last
> but not least the CDM-check enabling procedure is fixed to be independent
> from the non-related num_lanes field state.
> 
> Afterwards there is a series of cleanups. It concerns the changes like
> adding braces to the multi-line if-else constructions, trailing new-lines
> to the print format-string, dropping unnecessary version checking, and
> various code simplifications and optimizations.
> 
> New features like adding two-level DT bindings abstraction, adding better
> structured IP-core version interface, adding iATU regions size detection
> and the PCIe regions verification procedure, adding dma-ranges support,
> introducing a set of generic platform clocks and resets and finally adding
> Baikal-T1 PCIe interface support will be submitted in the next part of the
> series.
> 

Just a note that I won't be able to test this series again for some time. My
hardware is broken and it may take couple of weeks for me to get the
replacement. But I'll provide my reviews for all series.

Sorry for that!

Thanks,
Mani

> Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v2:
> - Fix the end address of the example in the patch log with
>   the INCREASE_REGION_SIZE flag usage fixup. It should be
>   0x1000FFFF and not 0x0000FFFF (@Manivannan).
> - Add the cleanup-on-error path to the dw_pcie_ep_init() function.
>   (@Manivannan)
> 
> Link: https://lore.kernel.org/linux-pci/20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v3:
> - Convert region variable type to u32 in order to fix the implicit type
>   conversion peculiarity. (@kbot)
> - Rebase onto v5.18-rc6.
> 
> Link: https://lore.kernel.org/linux-pci/20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v4:
> - Move the patch "PCI: dwc: Deallocate EPC memory on EP init error" to
>   being applied before the cleanup patches.
> - Add a new fixes patch: "PCI: dwc: Enable CDM-check independently from
>   the num_lanes value".
> - Add a new cleanup patch: "PCI: dwc: Organize local variables usage".
> - Add a new cleanup patch: "PCI: dwc: Re-use local pointer to the
>   resource data".
> - Add a new cleanup patch: "PCI: dwc: Add start_link/stop_link inliners".
> - Add a new cleanup patch: "PCI: dwc: Move io_cfg_atu_shared to the Root
>   Port descriptor".
> - Add a new cleanup patch: "PCI: dwc: Add dw_ prefix to the pcie_port
>   structure name".
> - Drop the patch "PCI: dwc: Don't use generic IO-ops for DBI-space
>   access". (@Rob)
> - Drop Manivannan tested tag from the changed patches.
> - Rebase onto v5.18.
> 
> Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v5:
> - Just resend the series.
> - Rebase onto v5.19-rcX.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: "Krzysztof Wilczyński" <kw@linux.com>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: linux-pci@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> 
> Serge Semin (18):
>   PCI: dwc: Stop link in the host init error and de-initialization
>   PCI: dwc: Add unroll iATU space support to the regions disable method
>   PCI: dwc: Disable outbound windows for controllers with iATU
>   PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
>   PCI: dwc: Deallocate EPC memory on EP init error
>   PCI: dwc: Enable CDM-check independently from the num_lanes value
>   PCI: dwc: Add braces to the multi-line if-else statements
>   PCI: dwc: Add trailing new-line literals to the log messages
>   PCI: dwc: Discard IP-core version checking on unrolled iATU detection
>   PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()
>   PCI: dwc: Organize local variables usage
>   PCI: dwc: Re-use local pointer to the resource data
>   PCI: dwc: Add start_link/stop_link inliners
>   PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor
>   PCI: dwc: Add dw_ prefix to the pcie_port structure name
>   PCI: dwc-plat: Simplify the probe method return value handling
>   PCI: dwc-plat: Discard unused regmap pointer
>   PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration
> 
>  drivers/pci/controller/dwc/pci-dra7xx.c       |  12 +--
>  drivers/pci/controller/dwc/pci-exynos.c       |   6 +-
>  drivers/pci/controller/dwc/pci-imx6.c         |   6 +-
>  drivers/pci/controller/dwc/pci-keystone.c     |  20 ++--
>  .../pci/controller/dwc/pci-layerscape-ep.c    |  12 ---
>  drivers/pci/controller/dwc/pci-layerscape.c   |   2 +-
>  drivers/pci/controller/dwc/pci-meson.c        |   2 +-
>  drivers/pci/controller/dwc/pcie-al.c          |   6 +-
>  drivers/pci/controller/dwc/pcie-armada8k.c    |   4 +-
>  drivers/pci/controller/dwc/pcie-artpec6.c     |   4 +-
>  .../pci/controller/dwc/pcie-designware-ep.c   |  30 ++++--
>  .../pci/controller/dwc/pcie-designware-host.c | 102 ++++++++++--------
>  .../pci/controller/dwc/pcie-designware-plat.c |  25 ++---
>  drivers/pci/controller/dwc/pcie-designware.c  |  72 +++++++------
>  drivers/pci/controller/dwc/pcie-designware.h  |  46 +++++---
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c |   4 +-
>  drivers/pci/controller/dwc/pcie-fu740.c       |   2 +-
>  drivers/pci/controller/dwc/pcie-histb.c       |  10 +-
>  drivers/pci/controller/dwc/pcie-intel-gw.c    |   6 +-
>  drivers/pci/controller/dwc/pcie-keembay.c     |   4 +-
>  drivers/pci/controller/dwc/pcie-kirin.c       |   2 +-
>  drivers/pci/controller/dwc/pcie-qcom.c        |   4 +-
>  drivers/pci/controller/dwc/pcie-spear13xx.c   |   6 +-
>  drivers/pci/controller/dwc/pcie-tegra194.c    |  22 ++--
>  drivers/pci/controller/dwc/pcie-uniphier.c    |  10 +-
>  drivers/pci/controller/dwc/pcie-visconti.c    |   6 +-
>  26 files changed, 224 insertions(+), 201 deletions(-)
> 
> -- 
> 2.35.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 03/18] PCI: dwc: Disable outbound windows for controllers with iATU

[Serge Semin]

Hi Bjorn

On Mon, Jun 27, 2022 at 05:40:58PM -0500, Bjorn Helgaas wrote:
> [+cc Jonathan for pcie-al.c, Kishon for pci-keystone.c]
> 
> On Fri, Jun 24, 2022 at 05:34:13PM +0300, Serge Semin wrote:
> > In accordance with the dw_pcie_setup_rc() method semantics and judging by
> > what the comment added in commit dd193929d91e ("PCI: designware: Explain
> > why we don't program ATU for some platforms") states there are DWC
> > PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's
> > Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU
> > enabled and use it's own address translation approach implemented. In
> > these cases at the very least there is no point in touching the DW PCIe
> > iATU CSRs. Moreover depending on the vendor-specific address translation
> > implementation it might be even erroneous. So let's move the iATU windows
> > disabling procedure to being under the corresponding conditional statement
> > clause thus performing that procedure only if the iATU is expected to be
> > available on the platform.
> 

> Added Jonathan and Kishon to make sure pcie-al.c and pci-keystone.c
> (the only two drivers that override the default dw_child_pcie_ops)
> won't be broken by skipping the outbound window disable.

Makes sense. Thanks.

> 
> > Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset")
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
> >  1 file changed, 8 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index bc9a7df130ef..d4326aae5a32 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -543,7 +543,6 @@ static struct pci_ops dw_pcie_ops = {
> >  
> >  void dw_pcie_setup_rc(struct pcie_port *pp)
> >  {
> > -	int i;
> >  	u32 val, ctrl, num_ctrls;
> >  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> >  
> > @@ -594,19 +593,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> >  		PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
> >  	dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
> >  
> > -	/* Ensure all outbound windows are disabled so there are multiple matches */
> > -	for (i = 0; i < pci->num_ob_windows; i++)
> > -		dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
> > -
> >  	/*
> >  	 * If the platform provides its own child bus config accesses, it means
> >  	 * the platform uses its own address translation component rather than
> >  	 * ATU, so we should not program the ATU here.
> >  	 */
> >  	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> > -		int atu_idx = 0;
> > +		int i, atu_idx = 0;
> >  		struct resource_entry *entry;
> >  
> > +		/*
> > +		 * Ensure all outbound windows are disabled so there are
> > +		 * multiple matches
> 

> I know you only moved this comment and didn't change the wording, but
> do you know what it means?  What "multiple matches" is it talking
> about, and why are they important?

AFAIU the In/Out-bound windows disabling procedure is a kind of
cleanup-before-usage pattern. So if the DW PCIe controller has been
used by a bootloader with non-DT-based (dma-)ranges setup, and hasn't
been reset by the low-level driver, some windows can be left
opened/configured. It may cause unpleasant side effects on the further
controller utilization. Although I don't see much room for the bugs in
this part since the iATU setup is overwritten from lowest index to the
highest one afterwards anyway and in accordance with the HW ref.
manual the first-match region will be used for the CPU<->PCIe IOs
translation. Basically should we leave the in/out-bound windows setup
uncleared the only thing that may cause problems/unexpected IO results
is the not-overridden iATU regions. It won't be that much of the
problem, but more like an unexpected behaviour, for instance, a random
MWr/MRd TLPs (depending on the bootloader iATU setup) generation on an
attempt to access some MMIO ranges, which aren't supposed to be used
by the system anyway.

Anyway as Rob said in the commit 458ad06c4cdd ("PCI: dwc: Ensure all
outbound ATU windows are reset") indeed it won't hurt to perform the
cleanup. It shall make the system state more predictable.

> 
> I guess Rob previously moved it with 458ad06c4cdd ("PCI: dwc: Ensure
> all outbound ATU windows are reset") [1], and it looks like maybe the
> point is to *avoid* having an outbound transaction match multiple
> windows?  So maybe this comment should say this?
> 
>   Disable all outbound windows to make sure a transaction can't match
>   multiple windows.

You are right. I can fix the text on v6 of the series.

-Sergey

> 
> [1] https://git.kernel.org/linus/458ad06c4cdd
> 
> > +		 */
> > +		for (i = 0; i < pci->num_ob_windows; i++)
> > +			dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
> > +
> >  		/* Get last memory resource entry */
> >  		resource_list_for_each_entry(entry, &pp->bridge->windows) {
> >  			if (resource_type(entry->res) != IORESOURCE_MEM)
> > -- 
> > 2.35.1
> > 

Re: [PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[Serge Semin]

On Tue, Jun 28, 2022 at 12:28:03PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jun 24, 2022 at 05:34:10PM +0300, Serge Semin wrote:
> > This patchset is a first one in the series created in the framework of
> > my Baikal-T1 PCIe/eDMA-related work:
> > 
> > [1: In-progress v5] PCI: dwc: Various fixes and cleanups
> > Link: ---you are looking at it---
> > [2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support
> > Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru/
> > [3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support
> > Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru/
> > [4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support
> > Link: https://lore.kernel.org/linux-pci/20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru/
> > 
> > Note it is very recommended to merge the patchsets in the same order as
> > they are placed in the list above in order to prevent possible merge
> > conflicts. Nothing prevents them from being reviewed synchronously though.
> > Any tests are very welcome!
> > 
> > As it can be easily inferred from the patchset title, this series is about
> > the DW PCIe Root Port/Endpoint driver fixes and the code cleanups, where
> > fixes come before the cleanup patches. The patchset starts with adding the
> > stop_link() platform-specific method invocation in case of the PCIe host
> > probe procedure errors. It has been missing in the cleanup-on-error path
> > of the DW PCIe Host initialization method. After that the unrolled CSRs
> > layout is added to the iATU disable procedure. In third the disable iATU
> > procedure is fixed to be called only for the internal ATU as being
> > specific for the internal ATU implementation. Then the outbound iATU
> > extended region setup procedure is fixed to have the INCREASE_REGION_SIZE
> > flag set based on the limit-address - not the region size one. The last
> > but not least the CDM-check enabling procedure is fixed to be independent
> > from the non-related num_lanes field state.
> > 
> > Afterwards there is a series of cleanups. It concerns the changes like
> > adding braces to the multi-line if-else constructions, trailing new-lines
> > to the print format-string, dropping unnecessary version checking, and
> > various code simplifications and optimizations.
> > 
> > New features like adding two-level DT bindings abstraction, adding better
> > structured IP-core version interface, adding iATU regions size detection
> > and the PCIe regions verification procedure, adding dma-ranges support,
> > introducing a set of generic platform clocks and resets and finally adding
> > Baikal-T1 PCIe interface support will be submitted in the next part of the
> > series.
> > 
> 

> Just a note that I won't be able to test this series again for some time. My
> hardware is broken and it may take couple of weeks for me to get the
> replacement. But I'll provide my reviews for all series.
> 
> Sorry for that!

No worries. The series hasn't changed that much since then.
Thanks for review and for earlier testing anyway.

-Sergey

> 
> Thanks,
> Mani
> 
> > Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v2:
> > - Fix the end address of the example in the patch log with
> >   the INCREASE_REGION_SIZE flag usage fixup. It should be
> >   0x1000FFFF and not 0x0000FFFF (@Manivannan).
> > - Add the cleanup-on-error path to the dw_pcie_ep_init() function.
> >   (@Manivannan)
> > 
> > Link: https://lore.kernel.org/linux-pci/20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v3:
> > - Convert region variable type to u32 in order to fix the implicit type
> >   conversion peculiarity. (@kbot)
> > - Rebase onto v5.18-rc6.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v4:
> > - Move the patch "PCI: dwc: Deallocate EPC memory on EP init error" to
> >   being applied before the cleanup patches.
> > - Add a new fixes patch: "PCI: dwc: Enable CDM-check independently from
> >   the num_lanes value".
> > - Add a new cleanup patch: "PCI: dwc: Organize local variables usage".
> > - Add a new cleanup patch: "PCI: dwc: Re-use local pointer to the
> >   resource data".
> > - Add a new cleanup patch: "PCI: dwc: Add start_link/stop_link inliners".
> > - Add a new cleanup patch: "PCI: dwc: Move io_cfg_atu_shared to the Root
> >   Port descriptor".
> > - Add a new cleanup patch: "PCI: dwc: Add dw_ prefix to the pcie_port
> >   structure name".
> > - Drop the patch "PCI: dwc: Don't use generic IO-ops for DBI-space
> >   access". (@Rob)
> > - Drop Manivannan tested tag from the changed patches.
> > - Rebase onto v5.18.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v5:
> > - Just resend the series.
> > - Rebase onto v5.19-rcX.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > Cc: Jingoo Han <jingoohan1@gmail.com>
> > Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > Cc: "Krzysztof Wilczyński" <kw@linux.com>
> > Cc: Frank Li <Frank.Li@nxp.com>
> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Cc: linux-pci@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > 
> > Serge Semin (18):
> >   PCI: dwc: Stop link in the host init error and de-initialization
> >   PCI: dwc: Add unroll iATU space support to the regions disable method
> >   PCI: dwc: Disable outbound windows for controllers with iATU
> >   PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
> >   PCI: dwc: Deallocate EPC memory on EP init error
> >   PCI: dwc: Enable CDM-check independently from the num_lanes value
> >   PCI: dwc: Add braces to the multi-line if-else statements
> >   PCI: dwc: Add trailing new-line literals to the log messages
> >   PCI: dwc: Discard IP-core version checking on unrolled iATU detection
> >   PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()
> >   PCI: dwc: Organize local variables usage
> >   PCI: dwc: Re-use local pointer to the resource data
> >   PCI: dwc: Add start_link/stop_link inliners
> >   PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor
> >   PCI: dwc: Add dw_ prefix to the pcie_port structure name
> >   PCI: dwc-plat: Simplify the probe method return value handling
> >   PCI: dwc-plat: Discard unused regmap pointer
> >   PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration
> > 
> >  drivers/pci/controller/dwc/pci-dra7xx.c       |  12 +--
> >  drivers/pci/controller/dwc/pci-exynos.c       |   6 +-
> >  drivers/pci/controller/dwc/pci-imx6.c         |   6 +-
> >  drivers/pci/controller/dwc/pci-keystone.c     |  20 ++--
> >  .../pci/controller/dwc/pci-layerscape-ep.c    |  12 ---
> >  drivers/pci/controller/dwc/pci-layerscape.c   |   2 +-
> >  drivers/pci/controller/dwc/pci-meson.c        |   2 +-
> >  drivers/pci/controller/dwc/pcie-al.c          |   6 +-
> >  drivers/pci/controller/dwc/pcie-armada8k.c    |   4 +-
> >  drivers/pci/controller/dwc/pcie-artpec6.c     |   4 +-
> >  .../pci/controller/dwc/pcie-designware-ep.c   |  30 ++++--
> >  .../pci/controller/dwc/pcie-designware-host.c | 102 ++++++++++--------
> >  .../pci/controller/dwc/pcie-designware-plat.c |  25 ++---
> >  drivers/pci/controller/dwc/pcie-designware.c  |  72 +++++++------
> >  drivers/pci/controller/dwc/pcie-designware.h  |  46 +++++---
> >  drivers/pci/controller/dwc/pcie-dw-rockchip.c |   4 +-
> >  drivers/pci/controller/dwc/pcie-fu740.c       |   2 +-
> >  drivers/pci/controller/dwc/pcie-histb.c       |  10 +-
> >  drivers/pci/controller/dwc/pcie-intel-gw.c    |   6 +-
> >  drivers/pci/controller/dwc/pcie-keembay.c     |   4 +-
> >  drivers/pci/controller/dwc/pcie-kirin.c       |   2 +-
> >  drivers/pci/controller/dwc/pcie-qcom.c        |   4 +-
> >  drivers/pci/controller/dwc/pcie-spear13xx.c   |   6 +-
> >  drivers/pci/controller/dwc/pcie-tegra194.c    |  22 ++--
> >  drivers/pci/controller/dwc/pcie-uniphier.c    |  10 +-
> >  drivers/pci/controller/dwc/pcie-visconti.c    |   6 +-
> >  26 files changed, 224 insertions(+), 201 deletions(-)
> > 
> > -- 
> > 2.35.1
> > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்

Re: [PATCH RESEND v5 11/18] PCI: dwc: Organize local variables usage

[Bjorn Helgaas]

On Fri, Jun 24, 2022 at 05:34:21PM +0300, Serge Semin wrote:
> There are several places in the common DW PCIe code with incoherent local
> variables usage: a variable is defined and initialized with a structure
> field, but the structure pointer is de-referenced to access that field
> anyway; the local variable is defined and initialized but either used just
> once or not used afterwards in the main part of the subsequent method.
> It's mainly concerns the pcie_port.dev field. Let's fix that in the
> relevant places.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> ---
> 
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------
>  drivers/pci/controller/dwc/pcie-designware.c      |  8 +++-----
>  2 files changed, 9 insertions(+), 11 deletions(-)

> @@ -633,7 +633,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  		}
>  
>  		if (pci->num_ob_windows <= atu_idx)
> -			dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
> +			dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",

I dropped this hunk because of this:

  drivers/pci/controller/dwc/pcie-designware-host.c:634:13: error: ‘dev’ undeclared (first use in this function); did you mean ‘cdev’?
    634 |    dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",

>  				 pci->num_ob_windows);
>  	}
>  

Re: [PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[Bjorn Helgaas]

On Fri, Jun 24, 2022 at 05:34:10PM +0300, Serge Semin wrote:
> This patchset is a first one in the series created in the framework of
> my Baikal-T1 PCIe/eDMA-related work:
> 
> [1: In-progress v5] PCI: dwc: Various fixes and cleanups
> Link: ---you are looking at it---
> [2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support
> Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru/
> [3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support
> Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru/
> [4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support
> Link: https://lore.kernel.org/linux-pci/20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru/
> 
> Note it is very recommended to merge the patchsets in the same order as
> they are placed in the list above in order to prevent possible merge
> conflicts. Nothing prevents them from being reviewed synchronously though.
> Any tests are very welcome!
> 
> As it can be easily inferred from the patchset title, this series is about
> the DW PCIe Root Port/Endpoint driver fixes and the code cleanups, where
> fixes come before the cleanup patches. The patchset starts with adding the
> stop_link() platform-specific method invocation in case of the PCIe host
> probe procedure errors. It has been missing in the cleanup-on-error path
> of the DW PCIe Host initialization method. After that the unrolled CSRs
> layout is added to the iATU disable procedure. In third the disable iATU
> procedure is fixed to be called only for the internal ATU as being
> specific for the internal ATU implementation. Then the outbound iATU
> extended region setup procedure is fixed to have the INCREASE_REGION_SIZE
> flag set based on the limit-address - not the region size one. The last
> but not least the CDM-check enabling procedure is fixed to be independent
> from the non-related num_lanes field state.
> 
> Afterwards there is a series of cleanups. It concerns the changes like
> adding braces to the multi-line if-else constructions, trailing new-lines
> to the print format-string, dropping unnecessary version checking, and
> various code simplifications and optimizations.
> 
> New features like adding two-level DT bindings abstraction, adding better
> structured IP-core version interface, adding iATU regions size detection
> and the PCIe regions verification procedure, adding dma-ranges support,
> introducing a set of generic platform clocks and resets and finally adding
> Baikal-T1 PCIe interface support will be submitted in the next part of the
> series.
> 
> Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v2:
> - Fix the end address of the example in the patch log with
>   the INCREASE_REGION_SIZE flag usage fixup. It should be
>   0x1000FFFF and not 0x0000FFFF (@Manivannan).
> - Add the cleanup-on-error path to the dw_pcie_ep_init() function.
>   (@Manivannan)
> 
> Link: https://lore.kernel.org/linux-pci/20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v3:
> - Convert region variable type to u32 in order to fix the implicit type
>   conversion peculiarity. (@kbot)
> - Rebase onto v5.18-rc6.
> 
> Link: https://lore.kernel.org/linux-pci/20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v4:
> - Move the patch "PCI: dwc: Deallocate EPC memory on EP init error" to
>   being applied before the cleanup patches.
> - Add a new fixes patch: "PCI: dwc: Enable CDM-check independently from
>   the num_lanes value".
> - Add a new cleanup patch: "PCI: dwc: Organize local variables usage".
> - Add a new cleanup patch: "PCI: dwc: Re-use local pointer to the
>   resource data".
> - Add a new cleanup patch: "PCI: dwc: Add start_link/stop_link inliners".
> - Add a new cleanup patch: "PCI: dwc: Move io_cfg_atu_shared to the Root
>   Port descriptor".
> - Add a new cleanup patch: "PCI: dwc: Add dw_ prefix to the pcie_port
>   structure name".
> - Drop the patch "PCI: dwc: Don't use generic IO-ops for DBI-space
>   access". (@Rob)
> - Drop Manivannan tested tag from the changed patches.
> - Rebase onto v5.18.
> 
> Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru/
> Changelog v5:
> - Just resend the series.
> - Rebase onto v5.19-rcX.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: "Krzysztof Wilczyński" <kw@linux.com>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: linux-pci@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org

I applied these to pci/ctrl/dwc-fixes for now.  We'll have some tweaks
(to merge with previous dwc changes, if nothing else), but I pushed
this interim version since I'll be on vacation for a week or so.

Looks like some nice fixes and cleanups, thank you!

> Serge Semin (18):
>   PCI: dwc: Stop link in the host init error and de-initialization
>   PCI: dwc: Add unroll iATU space support to the regions disable method
>   PCI: dwc: Disable outbound windows for controllers with iATU
>   PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
>   PCI: dwc: Deallocate EPC memory on EP init error
>   PCI: dwc: Enable CDM-check independently from the num_lanes value
>   PCI: dwc: Add braces to the multi-line if-else statements
>   PCI: dwc: Add trailing new-line literals to the log messages
>   PCI: dwc: Discard IP-core version checking on unrolled iATU detection
>   PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()
>   PCI: dwc: Organize local variables usage
>   PCI: dwc: Re-use local pointer to the resource data
>   PCI: dwc: Add start_link/stop_link inliners
>   PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor
>   PCI: dwc: Add dw_ prefix to the pcie_port structure name
>   PCI: dwc-plat: Simplify the probe method return value handling
>   PCI: dwc-plat: Discard unused regmap pointer
>   PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration
> 
>  drivers/pci/controller/dwc/pci-dra7xx.c       |  12 +--
>  drivers/pci/controller/dwc/pci-exynos.c       |   6 +-
>  drivers/pci/controller/dwc/pci-imx6.c         |   6 +-
>  drivers/pci/controller/dwc/pci-keystone.c     |  20 ++--
>  .../pci/controller/dwc/pci-layerscape-ep.c    |  12 ---
>  drivers/pci/controller/dwc/pci-layerscape.c   |   2 +-
>  drivers/pci/controller/dwc/pci-meson.c        |   2 +-
>  drivers/pci/controller/dwc/pcie-al.c          |   6 +-
>  drivers/pci/controller/dwc/pcie-armada8k.c    |   4 +-
>  drivers/pci/controller/dwc/pcie-artpec6.c     |   4 +-
>  .../pci/controller/dwc/pcie-designware-ep.c   |  30 ++++--
>  .../pci/controller/dwc/pcie-designware-host.c | 102 ++++++++++--------
>  .../pci/controller/dwc/pcie-designware-plat.c |  25 ++---
>  drivers/pci/controller/dwc/pcie-designware.c  |  72 +++++++------
>  drivers/pci/controller/dwc/pcie-designware.h  |  46 +++++---
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c |   4 +-
>  drivers/pci/controller/dwc/pcie-fu740.c       |   2 +-
>  drivers/pci/controller/dwc/pcie-histb.c       |  10 +-
>  drivers/pci/controller/dwc/pcie-intel-gw.c    |   6 +-
>  drivers/pci/controller/dwc/pcie-keembay.c     |   4 +-
>  drivers/pci/controller/dwc/pcie-kirin.c       |   2 +-
>  drivers/pci/controller/dwc/pcie-qcom.c        |   4 +-
>  drivers/pci/controller/dwc/pcie-spear13xx.c   |   6 +-
>  drivers/pci/controller/dwc/pcie-tegra194.c    |  22 ++--
>  drivers/pci/controller/dwc/pcie-uniphier.c    |  10 +-
>  drivers/pci/controller/dwc/pcie-visconti.c    |   6 +-
>  26 files changed, 224 insertions(+), 201 deletions(-)
> 
> -- 
> 2.35.1
> 

Re: [PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[Serge Semin]

On Tue, Jun 28, 2022 at 06:35:27PM -0500, Bjorn Helgaas wrote:
> On Fri, Jun 24, 2022 at 05:34:10PM +0300, Serge Semin wrote:
> > This patchset is a first one in the series created in the framework of
> > my Baikal-T1 PCIe/eDMA-related work:
> > 
> > [1: In-progress v5] PCI: dwc: Various fixes and cleanups
> > Link: ---you are looking at it---
> > [2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support
> > Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru/
> > [3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support
> > Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru/
> > [4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support
> > Link: https://lore.kernel.org/linux-pci/20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru/
> > 
> > Note it is very recommended to merge the patchsets in the same order as
> > they are placed in the list above in order to prevent possible merge
> > conflicts. Nothing prevents them from being reviewed synchronously though.
> > Any tests are very welcome!
> > 
> > As it can be easily inferred from the patchset title, this series is about
> > the DW PCIe Root Port/Endpoint driver fixes and the code cleanups, where
> > fixes come before the cleanup patches. The patchset starts with adding the
> > stop_link() platform-specific method invocation in case of the PCIe host
> > probe procedure errors. It has been missing in the cleanup-on-error path
> > of the DW PCIe Host initialization method. After that the unrolled CSRs
> > layout is added to the iATU disable procedure. In third the disable iATU
> > procedure is fixed to be called only for the internal ATU as being
> > specific for the internal ATU implementation. Then the outbound iATU
> > extended region setup procedure is fixed to have the INCREASE_REGION_SIZE
> > flag set based on the limit-address - not the region size one. The last
> > but not least the CDM-check enabling procedure is fixed to be independent
> > from the non-related num_lanes field state.
> > 
> > Afterwards there is a series of cleanups. It concerns the changes like
> > adding braces to the multi-line if-else constructions, trailing new-lines
> > to the print format-string, dropping unnecessary version checking, and
> > various code simplifications and optimizations.
> > 
> > New features like adding two-level DT bindings abstraction, adding better
> > structured IP-core version interface, adding iATU regions size detection
> > and the PCIe regions verification procedure, adding dma-ranges support,
> > introducing a set of generic platform clocks and resets and finally adding
> > Baikal-T1 PCIe interface support will be submitted in the next part of the
> > series.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220324012524.16784-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v2:
> > - Fix the end address of the example in the patch log with
> >   the INCREASE_REGION_SIZE flag usage fixup. It should be
> >   0x1000FFFF and not 0x0000FFFF (@Manivannan).
> > - Add the cleanup-on-error path to the dw_pcie_ep_init() function.
> >   (@Manivannan)
> > 
> > Link: https://lore.kernel.org/linux-pci/20220503212300.30105-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v3:
> > - Convert region variable type to u32 in order to fix the implicit type
> >   conversion peculiarity. (@kbot)
> > - Rebase onto v5.18-rc6.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220517125058.18488-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v4:
> > - Move the patch "PCI: dwc: Deallocate EPC memory on EP init error" to
> >   being applied before the cleanup patches.
> > - Add a new fixes patch: "PCI: dwc: Enable CDM-check independently from
> >   the num_lanes value".
> > - Add a new cleanup patch: "PCI: dwc: Organize local variables usage".
> > - Add a new cleanup patch: "PCI: dwc: Re-use local pointer to the
> >   resource data".
> > - Add a new cleanup patch: "PCI: dwc: Add start_link/stop_link inliners".
> > - Add a new cleanup patch: "PCI: dwc: Move io_cfg_atu_shared to the Root
> >   Port descriptor".
> > - Add a new cleanup patch: "PCI: dwc: Add dw_ prefix to the pcie_port
> >   structure name".
> > - Drop the patch "PCI: dwc: Don't use generic IO-ops for DBI-space
> >   access". (@Rob)
> > - Drop Manivannan tested tag from the changed patches.
> > - Rebase onto v5.18.
> > 
> > Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru/
> > Changelog v5:
> > - Just resend the series.
> > - Rebase onto v5.19-rcX.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > Cc: Jingoo Han <jingoohan1@gmail.com>
> > Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > Cc: "Krzysztof Wilczyński" <kw@linux.com>
> > Cc: Frank Li <Frank.Li@nxp.com>
> > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Cc: linux-pci@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> 

> I applied these to pci/ctrl/dwc-fixes for now.  We'll have some tweaks
> (to merge with previous dwc changes, if nothing else), but I pushed
> this interim version 

I've got three more DW PCIe+eDMA based patchsets to review and merge in.
As I noted in the cover letter and graphically represented here:
Link: https://lore.kernel.org/linux-pci/20220616152048.gcqacgs2ed66vsl4@mobilestation/
the last series depends on the previous changes and the changes
introduced by Frank Li. The Frank' work has been merged in into the
branch 'pci/edma' of your repo. Could you please move my patchset(s)
there too in order to avoid merge conflicts in future?

> since I'll be on vacation for a week or so.
> 

* Sigh... I have a feeling one more merge window will pass with
my patchsets hanging out in limbo.

> Looks like some nice fixes and cleanups, thank you!

Thanks.

-Sergey

> 
> > Serge Semin (18):
> >   PCI: dwc: Stop link in the host init error and de-initialization
> >   PCI: dwc: Add unroll iATU space support to the regions disable method
> >   PCI: dwc: Disable outbound windows for controllers with iATU
> >   PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
> >   PCI: dwc: Deallocate EPC memory on EP init error
> >   PCI: dwc: Enable CDM-check independently from the num_lanes value
> >   PCI: dwc: Add braces to the multi-line if-else statements
> >   PCI: dwc: Add trailing new-line literals to the log messages
> >   PCI: dwc: Discard IP-core version checking on unrolled iATU detection
> >   PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()
> >   PCI: dwc: Organize local variables usage
> >   PCI: dwc: Re-use local pointer to the resource data
> >   PCI: dwc: Add start_link/stop_link inliners
> >   PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor
> >   PCI: dwc: Add dw_ prefix to the pcie_port structure name
> >   PCI: dwc-plat: Simplify the probe method return value handling
> >   PCI: dwc-plat: Discard unused regmap pointer
> >   PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration
> > 
> >  drivers/pci/controller/dwc/pci-dra7xx.c       |  12 +--
> >  drivers/pci/controller/dwc/pci-exynos.c       |   6 +-
> >  drivers/pci/controller/dwc/pci-imx6.c         |   6 +-
> >  drivers/pci/controller/dwc/pci-keystone.c     |  20 ++--
> >  .../pci/controller/dwc/pci-layerscape-ep.c    |  12 ---
> >  drivers/pci/controller/dwc/pci-layerscape.c   |   2 +-
> >  drivers/pci/controller/dwc/pci-meson.c        |   2 +-
> >  drivers/pci/controller/dwc/pcie-al.c          |   6 +-
> >  drivers/pci/controller/dwc/pcie-armada8k.c    |   4 +-
> >  drivers/pci/controller/dwc/pcie-artpec6.c     |   4 +-
> >  .../pci/controller/dwc/pcie-designware-ep.c   |  30 ++++--
> >  .../pci/controller/dwc/pcie-designware-host.c | 102 ++++++++++--------
> >  .../pci/controller/dwc/pcie-designware-plat.c |  25 ++---
> >  drivers/pci/controller/dwc/pcie-designware.c  |  72 +++++++------
> >  drivers/pci/controller/dwc/pcie-designware.h  |  46 +++++---
> >  drivers/pci/controller/dwc/pcie-dw-rockchip.c |   4 +-
> >  drivers/pci/controller/dwc/pcie-fu740.c       |   2 +-
> >  drivers/pci/controller/dwc/pcie-histb.c       |  10 +-
> >  drivers/pci/controller/dwc/pcie-intel-gw.c    |   6 +-
> >  drivers/pci/controller/dwc/pcie-keembay.c     |   4 +-
> >  drivers/pci/controller/dwc/pcie-kirin.c       |   2 +-
> >  drivers/pci/controller/dwc/pcie-qcom.c        |   4 +-
> >  drivers/pci/controller/dwc/pcie-spear13xx.c   |   6 +-
> >  drivers/pci/controller/dwc/pcie-tegra194.c    |  22 ++--
> >  drivers/pci/controller/dwc/pcie-uniphier.c    |  10 +-
> >  drivers/pci/controller/dwc/pcie-visconti.c    |   6 +-
> >  26 files changed, 224 insertions(+), 201 deletions(-)
> > 
> > -- 
> > 2.35.1
> > 

Re: [PATCH RESEND v5 11/18] PCI: dwc: Organize local variables usage

[Serge Semin]

On Tue, Jun 28, 2022 at 06:33:27PM -0500, Bjorn Helgaas wrote:
> On Fri, Jun 24, 2022 at 05:34:21PM +0300, Serge Semin wrote:
> > There are several places in the common DW PCIe code with incoherent local
> > variables usage: a variable is defined and initialized with a structure
> > field, but the structure pointer is de-referenced to access that field
> > anyway; the local variable is defined and initialized but either used just
> > once or not used afterwards in the main part of the subsequent method.
> > It's mainly concerns the pcie_port.dev field. Let's fix that in the
> > relevant places.
> > 
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > 
> > ---
> > 
> > Changelog v4:
> > - This is a new patch created on the v4 lap of the series.
> > ---
> >  drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------
> >  drivers/pci/controller/dwc/pcie-designware.c      |  8 +++-----
> >  2 files changed, 9 insertions(+), 11 deletions(-)
> 
> > @@ -633,7 +633,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> >  		}
> >  
> >  		if (pci->num_ob_windows <= atu_idx)
> > -			dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
> > +			dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",
> 

> I dropped this hunk because of this:
> 
>   drivers/pci/controller/dwc/pcie-designware-host.c:634:13: error: ‘dev’ undeclared (first use in this function); did you mean ‘cdev’?
>     634 |    dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",
> 

Right. It must have been fixed by the auto-merging procedure of my
local working git-dir. Thanks.

-Sergey

> >  				 pci->num_ob_windows);
> >  	}
> >  

Re: [PATCH RESEND v5 00/18] PCI: dwc: Various fixes and cleanups

[Serge Semin]

Hi Bjorn.

On Wed, Jun 29, 2022 at 04:38:36AM +0300, Serge Semin wrote:
> On Tue, Jun 28, 2022 at 06:35:27PM -0500, Bjorn Helgaas wrote:
> > On Fri, Jun 24, 2022 at 05:34:10PM +0300, Serge Semin wrote:
> > > This patchset is a first one in the series created in the framework of
> > > my Baikal-T1 PCIe/eDMA-related work:
> > > 
> > > [1: In-progress v5] PCI: dwc: Various fixes and cleanups
> > > Link: ---you are looking at it---
> > > [2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support
> > > Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@baikalelectronics.ru/
> > > [3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support
> > > Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru/
> > > [4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support
> > > Link: https://lore.kernel.org/linux-pci/20220610091459.17612-1-Sergey.Semin@baikalelectronics.ru/
> > > 
> > > Note it is very recommended to merge the patchsets in the same order as
> > > they are placed in the list above in order to prevent possible merge
> > > conflicts. Nothing prevents them from being reviewed synchronously though.
> > > Any tests are very welcome!
> > > 
> > > [...]
> > > 
> > > Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru/
> > > Changelog v5:
> > > - Just resend the series.
> > > - Rebase onto v5.19-rcX.
> > > 
> > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > > Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
> > > Cc: Jingoo Han <jingoohan1@gmail.com>
> > > Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > > Cc: "Krzysztof Wilczyński" <kw@linux.com>
> > > Cc: Frank Li <Frank.Li@nxp.com>
> > > Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > Cc: linux-pci@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > 
> 

> > I applied these to pci/ctrl/dwc-fixes for now.  We'll have some tweaks
> > (to merge with previous dwc changes, if nothing else), but I pushed
> > this interim version 
> 
> I've got three more DW PCIe+eDMA based patchsets to review and merge in.
> As I noted in the cover letter and graphically represented here:
> Link: https://lore.kernel.org/linux-pci/20220616152048.gcqacgs2ed66vsl4@mobilestation/
> the last series depends on the previous changes and the changes
> introduced by Frank Li. The Frank' work has been merged in into the
> branch 'pci/edma' of your repo. Could you please move my patchset(s)
> there too in order to avoid merge conflicts in future?

Are you back from vacation yet? If so please consider the request
above.

-Sergey

> 
> > since I'll be on vacation for a week or so.
> > 
> 
> * Sigh... I have a feeling one more merge window will pass with
> my patchsets hanging out in limbo.
> 
> > Looks like some nice fixes and cleanups, thank you!
> 
> Thanks.
> 
> -Sergey
> 
> > 
> > > Serge Semin (18):
> > >   PCI: dwc: Stop link in the host init error and de-initialization
> > >   PCI: dwc: Add unroll iATU space support to the regions disable method
> > >   PCI: dwc: Disable outbound windows for controllers with iATU
> > >   PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
> > >   PCI: dwc: Deallocate EPC memory on EP init error
> > >   PCI: dwc: Enable CDM-check independently from the num_lanes value
> > >   PCI: dwc: Add braces to the multi-line if-else statements
> > >   PCI: dwc: Add trailing new-line literals to the log messages
> > >   PCI: dwc: Discard IP-core version checking on unrolled iATU detection
> > >   PCI: dwc: Convert Link-up status method to using dw_pcie_readl_dbi()
> > >   PCI: dwc: Organize local variables usage
> > >   PCI: dwc: Re-use local pointer to the resource data
> > >   PCI: dwc: Add start_link/stop_link inliners
> > >   PCI: dwc: Move io_cfg_atu_shared to the Root Port descriptor
> > >   PCI: dwc: Add dw_ prefix to the pcie_port structure name
> > >   PCI: dwc-plat: Simplify the probe method return value handling
> > >   PCI: dwc-plat: Discard unused regmap pointer
> > >   PCI: dwc-plat: Drop dw_plat_pcie_of_match forward declaration
> > > 
> > >  drivers/pci/controller/dwc/pci-dra7xx.c       |  12 +--
> > >  drivers/pci/controller/dwc/pci-exynos.c       |   6 +-
> > >  drivers/pci/controller/dwc/pci-imx6.c         |   6 +-
> > >  drivers/pci/controller/dwc/pci-keystone.c     |  20 ++--
> > >  .../pci/controller/dwc/pci-layerscape-ep.c    |  12 ---
> > >  drivers/pci/controller/dwc/pci-layerscape.c   |   2 +-
> > >  drivers/pci/controller/dwc/pci-meson.c        |   2 +-
> > >  drivers/pci/controller/dwc/pcie-al.c          |   6 +-
> > >  drivers/pci/controller/dwc/pcie-armada8k.c    |   4 +-
> > >  drivers/pci/controller/dwc/pcie-artpec6.c     |   4 +-
> > >  .../pci/controller/dwc/pcie-designware-ep.c   |  30 ++++--
> > >  .../pci/controller/dwc/pcie-designware-host.c | 102 ++++++++++--------
> > >  .../pci/controller/dwc/pcie-designware-plat.c |  25 ++---
> > >  drivers/pci/controller/dwc/pcie-designware.c  |  72 +++++++------
> > >  drivers/pci/controller/dwc/pcie-designware.h  |  46 +++++---
> > >  drivers/pci/controller/dwc/pcie-dw-rockchip.c |   4 +-
> > >  drivers/pci/controller/dwc/pcie-fu740.c       |   2 +-
> > >  drivers/pci/controller/dwc/pcie-histb.c       |  10 +-
> > >  drivers/pci/controller/dwc/pcie-intel-gw.c    |   6 +-
> > >  drivers/pci/controller/dwc/pcie-keembay.c     |   4 +-
> > >  drivers/pci/controller/dwc/pcie-kirin.c       |   2 +-
> > >  drivers/pci/controller/dwc/pcie-qcom.c        |   4 +-
> > >  drivers/pci/controller/dwc/pcie-spear13xx.c   |   6 +-
> > >  drivers/pci/controller/dwc/pcie-tegra194.c    |  22 ++--
> > >  drivers/pci/controller/dwc/pcie-uniphier.c    |  10 +-
> > >  drivers/pci/controller/dwc/pcie-visconti.c    |   6 +-
> > >  26 files changed, 224 insertions(+), 201 deletions(-)
> > > 
> > > -- 
> > > 2.35.1
> > >