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Wed, 29 Jun 2022 20:21:17 +0000 (GMT) X-AuditID: cbfec370-a83ff70000002615-fa-62bcb43d0da7 Received: from SSI-EX4.ssi.samsung.com ( [105.128.2.146]) by ussmgxs2new.samsung.com (USCPEXMTA) with SMTP id 61.7A.57470.D34BCB26; Wed, 29 Jun 2022 16:21:17 -0400 (EDT) Received: from SSI-EX3.ssi.samsung.com (105.128.2.228) by SSI-EX4.ssi.samsung.com (105.128.2.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Wed, 29 Jun 2022 13:21:16 -0700 Received: from SSI-EX3.ssi.samsung.com ([105.128.5.228]) by SSI-EX3.ssi.samsung.com ([105.128.5.228]) with mapi id 15.01.2375.024; Wed, 29 Jun 2022 13:21:16 -0700 From: Adam Manzanares To: Dan Williams CC: "linux-cxl@vger.kernel.org" , "hch@infradead.org" , "alison.schofield@intel.com" , "nvdimm@lists.linux.dev" , "linux-pci@vger.kernel.org" , "patches@lists.linux.dev" Subject: Re: [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Thread-Topic: [PATCH 05/46] cxl/core: Drop ->platform_res attribute for root decoders Thread-Index: AQHYi/XJZNdlvVrhU0SI5d+SQ3FK1Q== Date: Wed, 29 Jun 2022 20:21:16 +0000 Message-ID: <20220629202116.GC1140419@bgt-140510-bm01> In-Reply-To: <165603873619.551046.791596854070136223.stgit@dwillia2-xfh> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [105.128.2.176] Content-Type: text/plain; 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The tracking of that available > capacity can be done in iomem_resource directly. As a result, root > decoders no longer need to host their own resource tree. The > current ->platform_res attribute was added prematurely. >=20 > Otherwise, ->hpa_range fills the role of conveying the current decode > range of the decoder. >=20 > Signed-off-by: Dan Williams > --- > drivers/cxl/acpi.c | 17 ++++++++++------- > drivers/cxl/core/pci.c | 8 +------- > drivers/cxl/core/port.c | 30 +++++++----------------------- > drivers/cxl/cxl.h | 6 +----- > 4 files changed, 19 insertions(+), 42 deletions(-) >=20 > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > index 40286f5df812..951695cdb455 100644 > --- a/drivers/cxl/acpi.c > +++ b/drivers/cxl/acpi.c > @@ -108,8 +108,10 @@ static int cxl_parse_cfmws(union acpi_subtable_heade= rs *header, void *arg, > =20 > cxld->flags =3D cfmws_to_decoder_flags(cfmws->restrictions); > cxld->target_type =3D CXL_DECODER_EXPANDER; > - cxld->platform_res =3D (struct resource)DEFINE_RES_MEM(cfmws->base_hpa, > - cfmws->window_size); > + cxld->hpa_range =3D (struct range) { > + .start =3D cfmws->base_hpa, > + .end =3D cfmws->base_hpa + cfmws->window_size - 1, > + }; > cxld->interleave_ways =3D CFMWS_INTERLEAVE_WAYS(cfmws); > cxld->interleave_granularity =3D CFMWS_INTERLEAVE_GRANULARITY(cfmws); > =20 > @@ -119,13 +121,14 @@ static int cxl_parse_cfmws(union acpi_subtable_head= ers *header, void *arg, > else > rc =3D cxl_decoder_autoremove(dev, cxld); > if (rc) { > - dev_err(dev, "Failed to add decoder for %pr\n", > - &cxld->platform_res); > + dev_err(dev, "Failed to add decoder for [%#llx - %#llx]\n", > + cxld->hpa_range.start, cxld->hpa_range.end); Minor nit, should we add range in our debug message? + dev_err(dev, "Failed to add decoder for range [%#llx - %#llx]\n", > return 0; > } > - dev_dbg(dev, "add: %s node: %d range %pr\n", dev_name(&cxld->dev), > - phys_to_target_node(cxld->platform_res.start), > - &cxld->platform_res); > + dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n", > + dev_name(&cxld->dev), > + phys_to_target_node(cxld->hpa_range.start), > + cxld->hpa_range.start, cxld->hpa_range.end); > =20 > return 0; > } > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index c4c99ff7b55e..7672789c3225 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -225,7 +225,6 @@ static int dvsec_range_allowed(struct device *dev, vo= id *arg) > { > struct range *dev_range =3D arg; > struct cxl_decoder *cxld; > - struct range root_range; > =20 > if (!is_root_decoder(dev)) > return 0; > @@ -237,12 +236,7 @@ static int dvsec_range_allowed(struct device *dev, v= oid *arg) > if (!(cxld->flags & CXL_DECODER_F_RAM)) > return 0; > =20 > - root_range =3D (struct range) { > - .start =3D cxld->platform_res.start, > - .end =3D cxld->platform_res.end, > - }; > - > - return range_contains(&root_range, dev_range); > + return range_contains(&cxld->hpa_range, dev_range); > } > =20 > static void disable_hdm(void *_cxlhdm) > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 98bcbbd59a75..b51eb41aa839 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -73,29 +73,17 @@ static ssize_t start_show(struct device *dev, struct = device_attribute *attr, > char *buf) > { > struct cxl_decoder *cxld =3D to_cxl_decoder(dev); > - u64 start; > =20 > - if (is_root_decoder(dev)) > - start =3D cxld->platform_res.start; > - else > - start =3D cxld->hpa_range.start; > - > - return sysfs_emit(buf, "%#llx\n", start); > + return sysfs_emit(buf, "%#llx\n", cxld->hpa_range.start); > } > static DEVICE_ATTR_ADMIN_RO(start); > =20 > static ssize_t size_show(struct device *dev, struct device_attribute *at= tr, > - char *buf) > + char *buf) > { > struct cxl_decoder *cxld =3D to_cxl_decoder(dev); > - u64 size; > - > - if (is_root_decoder(dev)) > - size =3D resource_size(&cxld->platform_res); > - else > - size =3D range_len(&cxld->hpa_range); > =20 > - return sysfs_emit(buf, "%#llx\n", size); > + return sysfs_emit(buf, "%#llx\n", range_len(&cxld->hpa_range)); > } > static DEVICE_ATTR_RO(size); > =20 > @@ -1233,7 +1221,10 @@ static struct cxl_decoder *cxl_decoder_alloc(struc= t cxl_port *port, > cxld->interleave_ways =3D 1; > cxld->interleave_granularity =3D PAGE_SIZE; > cxld->target_type =3D CXL_DECODER_EXPANDER; > - cxld->platform_res =3D (struct resource)DEFINE_RES_MEM(0, 0); > + cxld->hpa_range =3D (struct range) { > + .start =3D 0, > + .end =3D -1, > + }; > =20 > return cxld; > err: > @@ -1347,13 +1338,6 @@ int cxl_decoder_add_locked(struct cxl_decoder *cxl= d, int *target_map) > if (rc) > return rc; > =20 > - /* > - * Platform decoder resources should show up with a reasonable name. Al= l > - * other resources are just sub ranges within the main decoder resource= . > - */ > - if (is_root_decoder(dev)) > - cxld->platform_res.name =3D dev_name(dev); > - > return device_add(dev); > } > EXPORT_SYMBOL_NS_GPL(cxl_decoder_add_locked, CXL); > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 8256728cea8d..35ce17872fc1 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -197,7 +197,6 @@ enum cxl_decoder_type { > * struct cxl_decoder - CXL address range decode configuration > * @dev: this decoder's device > * @id: kernel device name id > - * @platform_res: address space resources considered by root decoder > * @hpa_range: Host physical address range mapped by this decoder > * @interleave_ways: number of cxl_dports in this decode > * @interleave_granularity: data stride per dport > @@ -210,10 +209,7 @@ enum cxl_decoder_type { > struct cxl_decoder { > struct device dev; > int id; > - union { > - struct resource platform_res; > - struct range hpa_range; > - }; > + struct range hpa_range; > int interleave_ways; > int interleave_granularity; > enum cxl_decoder_type target_type; >=20 >=20 Otherwise, looks good. Reviewed by: Adam Manzanares =