From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <bhelgaas@google.com>, <michals@xilinx.com>,
Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port
Date: Tue, 5 Jul 2022 16:26:44 +0530 [thread overview]
Message-ID: <20220705105646.16980-1-bharat.kumar.gogada@xilinx.com> (raw)
Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
to enable and handle legacy interrupts.
Changes in v6:
- Added of_device_get_match_data to identify CPM version.
- Used enum values to differentiate CPM version.
Bharat Kumar Gogada (2):
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
.../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++-
drivers/pci/controller/pcie-xilinx-cpm.c | 64 ++++++++++++++++++-
2 files changed, 98 insertions(+), 4 deletions(-)
--
2.17.1
next reply other threads:[~2022-07-05 10:58 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-05 10:56 Bharat Kumar Gogada [this message]
2022-07-05 10:56 ` [PATCH v6 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port Bharat Kumar Gogada
2022-07-05 10:56 ` [PATCH v6 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
2022-07-19 18:06 ` [PATCH v6 0/2] Add support for Xilinx " Gogada, Bharat Kumar
2022-07-22 19:24 ` Bjorn Helgaas
2022-07-25 4:41 ` Gogada, Bharat Kumar
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