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Wed, 20 Jul 2022 14:51:08 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v4 0/5] Add support for Axis, ARTPEC-8 PCIe driver Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim , Wangseok Lee X-Priority: 3 X-Content-Kind-Code: NORMAL X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p5> Date: Wed, 20 Jul 2022 14:51:08 +0900 X-CMS-MailID: 20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL X-CPGSPASS: Y X-CPGSPASS: Y CMS-TYPE: 102P X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGJsWRmVeSWpSXmKPExsWy7bCmhe6Z6deTDM7OM7FY0pRh8fKQpsX8 I+dYLXbPWM5kMXPqGWaL54dmMVt8alG1uPC0h83i5ax7bBYNPb9ZLY68+chssf/4SiaLy7vm sFmcnXeczWLCqm8sFm9+v2C3OLc406J17xF2i513TjBb3Dl8lsXi19Y/TA6iHmvmrWH0uL4u wGPBplKPTas62TyeXJnO5LF5Sb1H35ZVjB7Hb2xn8vi8SS6AMyrbJiM1MSW1SCE1Lzk/JTMv 3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwfoMyWFssScUqBQQGJxsZK+nU1RfmlJ qkJGfnGJrVJqQUpOgXmBXnFibnFpXrpeXmqJlaGBgZEpUGFCdsapY/8YC/4oV/ycvIC9gfGn TBcjJ4eEgInEwu0z2LoYuTiEBHYwSryYfI+xi5GDg1dAUOLvDmEQU1jASWJvdzBIuZCAksSO NfOYQWxhAX2J6yu6WUFsNgFdiX+LX7KB2CICn1klru8RBBnJLHCSUWL54fVsELt4JWa0P2WB sKUlti/fyghha0j8WNbLDGGLStxc/ZYdxn5/bD5UjYhE672zUDWCEg9+7oaKS0kseHKIFcKu ltj/9zcThN3AKNF/PxXkfgmgQ3dcNwYJ8wr4Slx8fg5sDIuAqkTn7DNQ57hInF2wCWwts4C8 xPa3c5hBWpkFNCXW79KHmKIsceQWC8wjDRt/s6OzmQX4JDoO/4WL75j3BOoYNYl5K3cyQ4yR kdj60n8Co9IsRCjPQrJ2FsLaBYzMqxjFUguKc9NTi40KjOARm5yfu4kRnMC13HYwTnn7Qe8Q IxMH4yFGCQ5mJRHep4XXk4R4UxIrq1KL8uOLSnNSiw8xmgI9PJFZSjQ5H5hD8kriDU0sDUzM zAzNjUwNzJXEeb1SNiQKCaQnlqRmp6YWpBbB9DFxcEo1MK01KWT+dXjPZlXt0NtCr48tVmnL EDt7Mz9DolWAK/Qe978PvtpTV1RIuf+wvRaR3l9gdEpIoEn3jfpF0YnLbquEHTyjcYnxcfaB q+8W1bvOOvYr8HxQuI3gMxPnF3F1gk46hw4z19scd2J48dNw3y61S2+2z777mD/Re0JY/e81 XtP6Sxds7WBYEJ0rtHPbrvkOX62dphtpX0q5fEfpcdMKnaO682IUo49dkq1iDA/YdeFf0d8w 9/132Ntn7Vg7radC0rc6O0FuQq1S9Ye/Gc+qlm4+Mbtxxekr2Xs3/d/1sb2/4ML0zWKXpjtv KHyx5NbZBaoleUnPT+U/1VtStXGXmOfGOxEhtrUvr9ccDxRUYinOSDTUYi4qTgQAQlQM7GkE AAA= DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800 References: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This v4 patchset is improvement several review comments received from patchset v3. Main changes since v3 [3]: dt-bindings: pci: Add ARTPEC-8 PCIe controller -add missing properties dt-bindings: phy: Add ARTPEC-8 PCIe phy -add "fsys-sysreg" to properties -modify the "lcpll-ref-clk" and "clocks" in properties "lcpll-ref-clk" is custom properties, so add 'vendor', type(enum), description Add the maxItem in clocks, add clock-names in properties PCI: axis: Add ARTPEC-8 PCIe controller driver -remove unnecessary enum type -fix indentation phy: Add ARTPEC-8 PCIe PHY driver -modify to use GENMASK -fix indentation -remove the driver data Main changes since v2 [2]: dt-bindings: pci: Add ARTPEC-8 PCIe controller -modify version history to fit the linux commit rule -remove 'Device Tree Bindings' on title -remove the interrupt-names, phy-names entries -remove '_clk' suffix -add the compatible entries on required -change node name to soc from artpec8 on examples dt-bindings: phy: Add ARTPEC-8 PCIe phy -modify version history to fit the linux commit rule -remove 'Device Tree Bindings' on title -remove clock-names entries -change node name to soc from artpec8 on excamples PCI: axis: Add ARTPEC-8 PCIe controller driver -add 'COMPILE_TEST' and improvement help on kconfig -reorder obj on makefile -use clk_bulk_api -remove unnecessary comment -redefine the ELBI register to distinguish between offset and bit definition -improvement order local variable of function -remove unnecessary local return variable phy: Add ARTPEC-8 PCIe PHY driver -remove unnecessary indentation -redefine local struct to statis const -add static const to struct that requires static const definition -remove wrappers on writel and readl Main changes since v1 [1]: -'make dt_binding_check' result improvement -Add the missing property list -improvement review comment of Krzysztof on driver code -change folder name of phy driver to axis from artpec [3] https://lore.kernel.org/lkml/20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7/T [2] https://lore.kernel.org/lkml/20220613015023epcms2p70e6700a99042d4deb560e40ab5397001@epcms2p7/T/ [1] https://lore.kernel.org/lkml/20220328014430epcms2p7063834feb0abdf2f38a62723c96c9ff1@epcms2p7/ -------------------------------------------------------------- This series patches include newly PCIe support for Axis ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications. PCIe controller driver and phy driver have been newly added. There is also a new MAINTAINER in the addition of phy driver. PCIe controller is designed based on Design-Ware PCIe controller IP and PCIe phy is desinged based on SAMSUNG PHY IP. It also includes modifications to the Design-Ware controller driver to run the 64bit-based ARTPEC-8 PCIe controller driver. It consists of 6 patches in total. This series has been tested on AXIS SW bring-up board with ARTPEC-8 chipset. -------------------------------------------------------------- Wangseok Lee (5): dt-bindings: pci: Add ARTPEC-8 PCIe controller dt-bindings: phy: Add ARTPEC-8 PCIe phy PCI: axis: Add ARTPEC-8 PCIe controller driver phy: Add ARTPEC-8 PCIe PHY driver MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers .../bindings/pci/axis,artpec8-pcie-ep.yaml | 138 ++++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 148 ++++ .../bindings/phy/axis,artpec8-pcie-phy.yaml | 85 +++ MAINTAINERS | 2 + drivers/pci/controller/dwc/Kconfig | 31 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec8.c | 788 +++++++++++++++++++++ drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/axis/Kconfig | 9 + drivers/phy/axis/Makefile | 2 + drivers/phy/axis/phy-artpec8-pcie.c | 753 ++++++++++++++++++++ 12 files changed, 1959 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml create mode 100644 drivers/pci/controller/dwc/pcie-artpec8.c create mode 100644 drivers/phy/axis/Kconfig create mode 100644 drivers/phy/axis/Makefile create mode 100644 drivers/phy/axis/phy-artpec8-pcie.c -- 2.9.5