From: Bjorn Helgaas <helgaas@kernel.org>
To: linux-pci@vger.kernel.org
Cc: "Vidya Sagar" <vidyas@nvidia.com>,
"Saheed O . Bolarinwa" <refactormyself@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rajat Jain" <rajatja@google.com>,
"Kenneth R . Crudup" <kenny@panix.com>,
"Kai-Heng Feng" <kai.heng.feng@canonical.com>,
"Abhishek Sahu" <abhsahu@nvidia.com>,
"Thierry Reding" <treding@nvidia.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Krishna Thota" <kthota@nvidia.com>,
"Manikanta Maddireddy" <mmaddireddy@nvidia.com>,
"Vidya Sagar" <sagar.tv@gmail.com>,
sagupta@nvidia.com, linux-kernel@vger.kernel.org,
"Bjorn Helgaas" <bhelgaas@google.com>
Subject: [PATCH 2/3] PCI/ASPM: Ignore L1 PM Substates if device lacks capability
Date: Tue, 4 Oct 2022 21:58:08 -0500 [thread overview]
Message-ID: <20221005025809.2247547-3-helgaas@kernel.org> (raw)
In-Reply-To: <20221005025809.2247547-1-helgaas@kernel.org>
From: Bjorn Helgaas <bhelgaas@google.com>
187f91db8237 ("PCI/ASPM: Remove struct aspm_register_info.l1ss_cap")
inadvertently removed a check for existence of the L1 PM Substates (L1SS)
Capability before reading it.
If there is no L1SS Capability, this means we mistakenly read PCI_COMMAND
and PCI_STATUS (config address 0x04) and interpret that as the PCI_L1SS_CAP
register, so we may incorrectly configure L1SS.
Make sure the L1SS Capability exists before trying to read it.
Fixes: 187f91db8237 ("PCI/ASPM: Remove struct aspm_register_info.l1ss_cap")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/pcie/aspm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 4535228e4a64..f12d117f44e0 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -560,6 +560,9 @@ static void aspm_l1ss_init(struct pcie_link_state *link)
u32 parent_l1ss_cap, child_l1ss_cap;
u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
+ if (!parent->l1ss || !child->l1ss)
+ return;
+
/* Setup L1 substate */
pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
&parent_l1ss_cap);
--
2.25.1
next prev parent reply other threads:[~2022-10-05 2:58 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 2:58 [PATCH 0/3] PCI/ASPM: Fix L1SS issues Bjorn Helgaas
2022-10-05 2:58 ` [PATCH 1/3] PCI/ASPM: Factor out L1 PM Substates configuration Bjorn Helgaas
2022-10-05 2:58 ` Bjorn Helgaas [this message]
2022-10-05 3:26 ` [PATCH 2/3] PCI/ASPM: Ignore L1 PM Substates if device lacks capability Sathyanarayanan Kuppuswamy
2022-10-05 11:07 ` Bjorn Helgaas
2022-10-05 2:58 ` [PATCH 3/3] PCI/ASPM: Correct LTR_L1.2_THRESHOLD computation Bjorn Helgaas
2022-10-05 3:28 ` [PATCH 0/3] PCI/ASPM: Fix L1SS issues Sathyanarayanan Kuppuswamy
2022-10-05 17:57 ` Bjorn Helgaas
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