From: Vadym Kochan <vadym.kochan@plvision.eu>
To: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Elad Nachman <enachman@marvell.com>,
Yuval Shaia <yshaia@marvell.com>,
Vadym Kochan <vadym.kochan@plvision.eu>
Subject: [PATCH 2/2] PCI: armada8k: Add MSI support for AC5 SoC
Date: Thu, 6 Oct 2022 14:11:10 +0300 [thread overview]
Message-ID: <20221006111110.8574-3-vadym.kochan@plvision.eu> (raw)
In-Reply-To: <20221006111110.8574-1-vadym.kochan@plvision.eu>
From: Yuval Shaia <yshaia@marvell.com>
AC5 requieres different handling for MSI as with armada8k.
Fix it by:
1. Enabling the relevant bits in init phase
2. Dispatch virtual IRQ handlers when MSI interrupts are received
Also enable/disable PCIE_APP_LTSSM for AC5.
Signed-off-by: Yuval Shaia <yshaia@marvell.com>
Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
---
drivers/pci/controller/dwc/pcie-armada8k.c | 28 ++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index b025d23bb058..c2a285e33e90 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -45,6 +45,7 @@ struct armada8k_pcie {
#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
#define PCIE_APP_LTSSM_EN BIT(2)
+#define PCIE_APP_LTSSM_EN_AC5 BIT(24)
#define PCIE_DEVICE_TYPE_SHIFT 4
#define PCIE_DEVICE_TYPE_MASK 0xF
#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
@@ -64,6 +65,7 @@ struct armada8k_pcie {
#define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13)
#define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14)
#define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15)
+#define PCIE_MSI_MASK_AC5 BIT(11)
#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
@@ -167,16 +169,30 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
static int armada8k_pcie_start_link(struct dw_pcie *pci)
{
+ struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
u32 reg;
/* Start LTSSM */
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
- reg |= PCIE_APP_LTSSM_EN;
+ if (pcie->pcie_type == MVPCIE_TYPE_AC5)
+ reg |= PCIE_APP_LTSSM_EN_AC5;
+ else
+ reg |= PCIE_APP_LTSSM_EN;
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
return 0;
}
+void ac5_pcie_msi_init(struct dw_pcie *pci)
+{
+ u32 val;
+
+ /* Set MSI bit in interrupt mask */
+ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
+ val |= PCIE_MSI_MASK_AC5;
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val);
+}
+
static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
{
u32 reg;
@@ -186,7 +202,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
- reg &= ~(PCIE_APP_LTSSM_EN);
+ if (pcie->pcie_type == MVPCIE_TYPE_AC5)
+ reg &= ~(PCIE_APP_LTSSM_EN_AC5);
+ else
+ reg &= ~(PCIE_APP_LTSSM_EN);
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
}
@@ -226,6 +245,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
}
+ if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == MVPCIE_TYPE_AC5))
+ ac5_pcie_msi_init(pci);
+
return 0;
}
@@ -242,6 +264,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
*/
val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
+ if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == MVPCIE_TYPE_AC5))
+ dw_handle_msi_irq(&pci->pp);
return IRQ_HANDLED;
}
--
2.17.1
next prev parent reply other threads:[~2022-10-06 11:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 11:11 [PATCH 0/2] PCI: armada8k: Add support for AC5 SoC Vadym Kochan
2022-10-06 11:11 ` [PATCH 1/2] PCI: armada8k: Add AC5 SoC support Vadym Kochan
2022-10-06 16:05 ` Bjorn Helgaas
2022-10-06 11:11 ` Vadym Kochan [this message]
2022-10-06 16:06 ` [PATCH 2/2] PCI: armada8k: Add MSI support for AC5 SoC Bjorn Helgaas
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