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Thu, 13 Oct 2022 10:57:14 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Date: Thu, 13 Oct 2022 23:27:09 +0530 Message-ID: <20221013175712.7539-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT016:EE_|CH0PR12MB5297:EE_ X-MS-Office365-Filtering-Correlation-Id: 96c065dd-d0db-49ba-8df6-08daad446b06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AYXrHcBCB01dtAPZCwCMcqfHLvNXSt2A5pBKn1hDhmapm7HXpjV/1V7mhDw61GjpamG5Df21DZOuL2e4AIBp+EWjaOZKpvYwmgBas3eRl7e5HCTa55tZru9/GjeDm/fJa5MPW6AgxZMSbzi7iERbXSPI5OwlOzAJ5v1utfuElqiUH8Sq36gUmoeEcjML1z+yitI/vQbaRFZ3WfCpCEAHI2MUh7ObxHE3jganaxECC23Yh6rtJpGlP3QplBg+f/8PfpkckHdPQFmB/az/11kdDgJ6soCuiHkH+emvcxVijf/O1pImnUMzYNfO4dXJI+VMBkfolXE1uLcGz44VvgP/urwa0QWPo/TESLnX2QDOEpMQQ3OLudKB7Qe35vxQuRCLgHQ4wRSJh6mtxtFyqAKYYsakUZ/yfttLYWVuYvKsJ5SgKLg2zYriz61MzNiRX6mj2Y3f6+Ulf5cTLrSePNNnH5nl103LBaRQPZR5soBRqPPQ88OP3rnETOTfhY5jBXq+vr6LXOXdTayDIPbFhOLpl6idhzwmkwsltE4laAKnNrwbjQpY0WLTaHTpVRz++vhoIEIyN7iTDgAUeYxrNsVXb9I8g1GZNjYFddmzt2FPS/ZserY8A2BhzLjf7084qByl/0fzhU+dEOsIvL/6w939Ycc0a09thPP0+gVYzaG6Urd2BN4GVPxljwJyL0dT7ioZ3Xyssjaz8VPzd4nTCGd7LDTAA+aT2g1wr3piiLlmh4MmUIyAQfgK+QjbReA6XIOk1K6bthQJSchCwYLAhBk81wFtRRPKN29mZCIKA/GPf88= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(346002)(376002)(396003)(451199015)(46966006)(40470700004)(36840700001)(82740400003)(6666004)(316002)(40480700001)(36756003)(356005)(7636003)(83380400001)(70586007)(70206006)(4326008)(8676002)(426003)(47076005)(40460700003)(7696005)(921005)(82310400005)(36860700001)(336012)(8936002)(2616005)(110136005)(7416002)(26005)(54906003)(41300700001)(478600001)(186003)(5660300002)(1076003)(86362001)(2906002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 17:57:38.9444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96c065dd-d0db-49ba-8df6-08daad446b06 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5297 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This series attempts to fix the issue with core register (Ex:- DBI) accesses causing system hang issues in platforms where there is a dependency on the availability of PCIe Reference clock from the host for their core initialization. This series is verified on Tegra194 & Tegra234 platforms. Manivannan, could you please verify on qcom platforms? V5: * Addressed review comments from Bjorn * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() * Skipped memory allocation if done already. This is to avoid freeing and then allocating again during PERST# toggles from the host. V4: * Addressed review comments from Bjorn and Manivannan * Added .ep_init_late() ops * Added patches to refactor code in qcom and tegra platforms Vidya Sagar (3): PCI: designware-ep: Fix DBI access before core init PCI: qcom-ep: Refactor EP initialization completion PCI: tegra194: Refactor EP initialization completion .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 10 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- 4 files changed, 97 insertions(+), 69 deletions(-) -- 2.17.1