From: Vidya Sagar <vidyas@nvidia.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>,
<mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>,
<ffclaire1224@gmail.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V3 06/21] PCI: tegra194: Refactor LTSSM state polling on surprise down
Date: Fri, 14 Oct 2022 00:08:39 +0530 [thread overview]
Message-ID: <20221013183854.21087-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com>
On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock ->
Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock
and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively.
So, the total time taken to transit from L0 to detect state is ~96 msec.
Hence, increase the poll time to 120 msec.
Disable the LTSSM state after it transits to detect to avoid LTSSM
toggling between polling and detect states.
tegra_pcie_dw_pme_turnoff() function is called in non-atomic context
only, so use the non-atomic poll function.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Addressed review comments from Bjorn
* Reworded the commit message
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++---------
1 file changed, 32 insertions(+), 23 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 69e11a74a0d7..897e2a22bcd3 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -141,7 +141,11 @@
#define APPL_DEBUG_PM_LINKST_IN_L0 0x11
#define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)
#define APPL_DEBUG_LTSSM_STATE_SHIFT 3
-#define LTSSM_STATE_PRE_DETECT 5
+#define LTSSM_STATE_DETECT_QUIET 0x00
+#define LTSSM_STATE_DETECT_ACT 0x08
+#define LTSSM_STATE_PRE_DETECT_QUIET 0x28
+#define LTSSM_STATE_DETECT_WAIT 0x30
+#define LTSSM_STATE_L2_IDLE 0xa8
#define APPL_RADM_STATUS 0xE4
#define APPL_PM_XMT_TURNOFF_STATE BIT(0)
@@ -210,7 +214,8 @@
#define PME_ACK_DELAY 100 /* 100 us */
#define PME_ACK_TIMEOUT 10000 /* 10 ms */
-#define LTSSM_TIMEOUT 50000 /* 50ms */
+#define LTSSM_DELAY 10000 /* 10 ms */
+#define LTSSM_TIMEOUT 120000 /* 120 ms */
#define GEN3_GEN4_EQ_PRESET_INIT 5
@@ -1663,23 +1668,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
data &= ~APPL_PINMUX_PEX_RST;
appl_writel(pcie, data, APPL_PINMUX);
+ err = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,
+ ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
+ ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
+ ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
+ ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT),
+ LTSSM_DELAY, LTSSM_TIMEOUT);
+ if (err)
+ dev_info(pcie->dev, "Link didn't go to detect state\n");
+
/*
- * Some cards do not go to detect state even after de-asserting
- * PERST#. So, de-assert LTSSM to bring link to detect state.
+ * Deassert LTSSM state to stop the state toggling between
+ * polling and detect.
*/
data = readl(pcie->appl_base + APPL_CTRL);
data &= ~APPL_CTRL_LTSSM_EN;
writel(data, pcie->appl_base + APPL_CTRL);
-
- err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
- data,
- ((data &
- APPL_DEBUG_LTSSM_STATE_MASK) >>
- APPL_DEBUG_LTSSM_STATE_SHIFT) ==
- LTSSM_STATE_PRE_DETECT,
- 1, LTSSM_TIMEOUT);
- if (err)
- dev_info(pcie->dev, "Link didn't go to detect state\n");
}
/*
* DBI registers may not be accessible after this as PLL-E would be
@@ -1769,19 +1773,24 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
if (pcie->ep_state == EP_STATE_DISABLED)
return;
- /* Disable LTSSM */
+ ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
+ ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
+ ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
+ ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
+ ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) ||
+ ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE),
+ LTSSM_DELAY, LTSSM_TIMEOUT);
+ if (ret)
+ dev_err(pcie->dev, "LTSSM state: 0x%x timeout: %d\n", val, ret);
+
+ /*
+ * Deassert LTSSM state to stop the state toggling between
+ * polling and detect.
+ */
val = appl_readl(pcie, APPL_CTRL);
val &= ~APPL_CTRL_LTSSM_EN;
appl_writel(pcie, val, APPL_CTRL);
- ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
- ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
- APPL_DEBUG_LTSSM_STATE_SHIFT) ==
- LTSSM_STATE_PRE_DETECT,
- 1, LTSSM_TIMEOUT);
- if (ret)
- dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
-
reset_control_assert(pcie->core_rst);
tegra_pcie_disable_phy(pcie);
--
2.17.1
next prev parent reply other threads:[~2022-10-13 18:42 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 18:38 [PATCH V3 00/21] Enhancements to pcie-tegra194 driver Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 01/21] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 02/21] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 03/21] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 04/21] PCI: tegra194: Handle errors in BPMP response Vidya Sagar
2023-01-13 15:15 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 05/21] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar
2022-10-13 18:38 ` Vidya Sagar [this message]
2022-10-13 18:38 ` [PATCH V3 07/21] PCI: tegra194: Disable direct speed change for EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 08/21] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar
2022-10-28 11:42 ` Vinod Koul
2022-10-28 11:49 ` Vidya Sagar
2022-10-28 12:13 ` Vinod Koul
2022-10-13 18:38 ` [PATCH V3 09/21] PCI: tegra194: Calibrate P2U for endpoint mode Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 10/21] PCI: tegra194: Free resources during controller deinitialization Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 11/21] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Vidya Sagar
2022-11-14 11:56 ` Lorenzo Pieralisi
2023-01-13 15:21 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 12/21] PCI: tegra194: Enable DMA interrupt Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 13/21] PCI: tegra194: Enable hardware hot reset mode in Endpoint Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 14/21] PCI: tegra194: Allow system suspend when the Endpoint link is not up Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 15/21] PCI: tegra194: Disable L1.2 capability of Tegra234 EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 16/21] PCI: tegra194: Set LTR message request before PCIe link up Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 17/21] PCI: tegra194: Reduce AXI slave timeout value Vidya Sagar
2023-01-13 15:31 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 18/21] PCI: tegra194: Don't force the device into the D0 state before L2 Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 19/21] PCI: tegra194: Free up EP resources during remove() Vidya Sagar
2023-01-13 15:28 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 20/21] dt-bindings: PCI: tegra194: Add monitor clock support Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 21/21] PCI: tegra194: Add core " Vidya Sagar
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