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From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Will Deacon <will@kernel.org>,
	linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jason Gunthorpe <jgg@mellanox.com>, Andrew Lunn <andrew@lunn.ch>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Ammar Faizi <ammarfaizi2@gnuweeb.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>,
	Santosh Shilimkar <ssantosh@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Vinod Koul <vkoul@kernel.org>, Sinan Kaya <okaya@kernel.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Shameerali Kolothum Thodi  <shameerali.kolothum.thodi@huawei.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>
Subject: [patch V2 38/40] irqchip/irq-mvebu-icu: Remove platform MSI leftovers
Date: Mon, 21 Nov 2022 15:40:15 +0100 (CET)	[thread overview]
Message-ID: <20221121140050.705171344@linutronix.de> (raw)
In-Reply-To: 20221121135653.208611233@linutronix.de

All related domains provide MSI parent functionality, so the fallback code
to the original platform MSI implementation is not longer required.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
 drivers/irqchip/irq-mvebu-icu.c |  213 +---------------------------------------
 1 file changed, 6 insertions(+), 207 deletions(-)

--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -129,196 +129,6 @@ static void mvebu_icu_init(struct mvebu_
 	writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al);
 }
 
-/* Start of area to be removed once all parent chips provide MSI parent */
-
-struct mvebu_icu_irq_data {
-	struct mvebu_icu *icu;
-	unsigned int icu_group;
-	unsigned int type;
-};
-
-static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
-{
-	struct irq_data *d = irq_get_irq_data(desc->irq);
-	struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d->domain);
-	struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
-	struct mvebu_icu *icu = icu_irqd->icu;
-	unsigned int icu_int;
-
-	if (msg->address_lo || msg->address_hi) {
-		/* One off initialization per domain */
-		mvebu_icu_init(icu, msi_data, msg);
-		/* Configure the ICU with irq number & type */
-		icu_int = msg->data | ICU_INT_ENABLE;
-		if (icu_irqd->type & IRQ_TYPE_EDGE_RISING)
-			icu_int |= ICU_IS_EDGE;
-		icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT;
-	} else {
-		/* De-configure the ICU */
-		icu_int = 0;
-	}
-
-	writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
-
-	/*
-	 * The SATA unit has 2 ports, and a dedicated ICU entry per
-	 * port. The ahci sata driver supports only one irq interrupt
-	 * per SATA unit. To solve this conflict, we configure the 2
-	 * SATA wired interrupts in the south bridge into 1 GIC
-	 * interrupt in the north bridge. Even if only a single port
-	 * is enabled, if sata node is enabled, both interrupts are
-	 * configured (regardless of which port is actually in use).
-	 */
-	if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) {
-		writel_relaxed(icu_int,
-			       icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
-		writel_relaxed(icu_int,
-			       icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
-	}
-}
-
-static struct irq_chip mvebu_icu_nsr_chip = {
-	.name			= "ICU-NSR",
-	.irq_mask		= irq_chip_mask_parent,
-	.irq_unmask		= irq_chip_unmask_parent,
-	.irq_eoi		= irq_chip_eoi_parent,
-	.irq_set_type		= irq_chip_set_type_parent,
-	.irq_set_affinity	= irq_chip_set_affinity_parent,
-};
-
-static struct irq_chip mvebu_icu_sei_chip = {
-	.name			= "ICU-SEI",
-	.irq_ack		= irq_chip_ack_parent,
-	.irq_mask		= irq_chip_mask_parent,
-	.irq_unmask		= irq_chip_unmask_parent,
-	.irq_set_type		= irq_chip_set_type_parent,
-	.irq_set_affinity	= irq_chip_set_affinity_parent,
-};
-
-static int
-mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
-			       unsigned long *hwirq, unsigned int *type)
-{
-	unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2;
-	struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d);
-	struct mvebu_icu *icu = msi_data->icu;
-
-	/* Check the count of the parameters in dt */
-	if (WARN_ON(fwspec->param_count != param_count)) {
-		dev_err(icu->dev, "wrong ICU parameter count %d\n",
-			fwspec->param_count);
-		return -EINVAL;
-	}
-
-	if (static_branch_unlikely(&legacy_bindings)) {
-		*hwirq = fwspec->param[1];
-		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
-		if (fwspec->param[0] != ICU_GRP_NSR) {
-			dev_err(icu->dev, "wrong ICU group type %x\n",
-				fwspec->param[0]);
-			return -EINVAL;
-		}
-	} else {
-		*hwirq = fwspec->param[0];
-		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
-
-		/*
-		 * The ICU receives level interrupts. While the NSR are also
-		 * level interrupts, SEI are edge interrupts. Force the type
-		 * here in this case. Please note that this makes the interrupt
-		 * handling unreliable.
-		 */
-		if (msi_data->subset_data->icu_group == ICU_GRP_SEI)
-			*type = IRQ_TYPE_EDGE_RISING;
-	}
-
-	if (*hwirq >= ICU_MAX_IRQS) {
-		dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int
-mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
-			   unsigned int nr_irqs, void *args)
-{
-	int err;
-	unsigned long hwirq;
-	struct irq_fwspec *fwspec = args;
-	struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(domain);
-	struct mvebu_icu *icu = msi_data->icu;
-	struct mvebu_icu_irq_data *icu_irqd;
-	struct irq_chip *chip = &mvebu_icu_nsr_chip;
-
-	icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL);
-	if (!icu_irqd)
-		return -ENOMEM;
-
-	err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq,
-					     &icu_irqd->type);
-	if (err) {
-		dev_err(icu->dev, "failed to translate ICU parameters\n");
-		goto free_irqd;
-	}
-
-	if (static_branch_unlikely(&legacy_bindings))
-		icu_irqd->icu_group = fwspec->param[0];
-	else
-		icu_irqd->icu_group = msi_data->subset_data->icu_group;
-	icu_irqd->icu = icu;
-
-	err = platform_msi_device_domain_alloc(domain, virq, nr_irqs);
-	if (err) {
-		dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
-		goto free_irqd;
-	}
-
-	/* Make sure there is no interrupt left pending by the firmware */
-	err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false);
-	if (err)
-		goto free_msi;
-
-	if (icu_irqd->icu_group == ICU_GRP_SEI)
-		chip = &mvebu_icu_sei_chip;
-
-	err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
-					    chip, icu_irqd);
-	if (err) {
-		dev_err(icu->dev, "failed to set the data to IRQ domain\n");
-		goto free_msi;
-	}
-
-	return 0;
-
-free_msi:
-	platform_msi_device_domain_free(domain, virq, nr_irqs);
-free_irqd:
-	kfree(icu_irqd);
-	return err;
-}
-
-static void
-mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
-			  unsigned int nr_irqs)
-{
-	struct irq_data *d = irq_get_irq_data(virq);
-	struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
-
-	kfree(icu_irqd);
-
-	platform_msi_device_domain_free(domain, virq, nr_irqs);
-}
-
-static const struct irq_domain_ops mvebu_icu_domain_ops = {
-	.translate = mvebu_icu_irq_domain_translate,
-	.alloc     = mvebu_icu_irq_domain_alloc,
-	.free      = mvebu_icu_irq_domain_free,
-};
-
-/* End of removal area */
-
 static int mvebu_icu_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
 			      unsigned int virq, irq_hw_number_t hwirq, msi_alloc_info_t *arg)
 {
@@ -448,9 +258,10 @@ static const struct of_device_id mvebu_i
 
 static int mvebu_icu_subset_probe(struct platform_device *pdev)
 {
+	const struct msi_domain_template *tmpl;
 	struct mvebu_icu_msi_data *msi_data;
 	struct device *dev = &pdev->dev;
-	struct irq_domain *irq_domain;
+	bool sei;
 
 	msi_data = devm_kzalloc(dev, sizeof(*msi_data), GFP_KERNEL);
 	if (!msi_data)
@@ -471,26 +282,14 @@ static int mvebu_icu_subset_probe(struct
 	if (!irq_domain_get_of_node(dev->msi.domain))
 		return -ENODEV;
 
-	if (irq_domain_is_msi_parent(dev->msi.domain)) {
-		bool sei = msi_data->subset_data->icu_group == ICU_GRP_SEI;
-		const struct msi_domain_template *tmpl;
-
-		tmpl = sei ? &mvebu_icu_sei_msi_template : &mvebu_icu_nsr_msi_template;
-
-		if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, tmpl,
-						  ICU_MAX_IRQS, NULL, msi_data))
-			return -ENOMEM;
-	}
+	sei = msi_data->subset_data->icu_group == ICU_GRP_SEI;
+	tmpl = sei ? &mvebu_icu_sei_msi_template : &mvebu_icu_nsr_msi_template;
 
-	irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS,
-							    mvebu_icu_write_msg,
-							    &mvebu_icu_domain_ops,
-							    msi_data);
-	if (!irq_domain) {
+	if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, tmpl,
+					  ICU_MAX_IRQS, NULL, msi_data)) {
 		dev_err(dev, "Failed to create ICU MSI domain\n");
 		return -ENOMEM;
 	}
-
 	return 0;
 }
 


  parent reply	other threads:[~2022-11-21 15:10 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-21 14:39 [patch V2 00/40] genirq, irqchip: Convert ARM MSI handling to per device MSI domains Thomas Gleixner
2022-11-21 14:39 ` [patch V2 01/40] irqchip/irq-mvebu-icu: Fix works by chance pointer assignment Thomas Gleixner
2022-11-24 12:50   ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 02/40] ACPI/IORT: Make prototype of iort_pmsi_get_dev_id() always available Thomas Gleixner
2022-11-21 15:13   ` Robin Murphy
2022-11-21 14:39 ` [patch V2 03/40] irqchip/gic-v2m: Include arm-gic-common.h Thomas Gleixner
2022-11-24 12:51   ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 04/40] irqchip/gic-v2m: Mark a few functions __init Thomas Gleixner
2022-11-24 12:54   ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 05/40] irqchip/ti-sci-inta: Fix kernel doc Thomas Gleixner
2022-11-24 12:54   ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 06/40] PCI/MSI: Provide static key for parent mask/unmask Thomas Gleixner
2022-11-24 13:04   ` Marc Zyngier
2022-11-24 13:17     ` Thomas Gleixner
2022-11-24 13:38       ` Marc Zyngier
2022-11-25  0:11         ` Thomas Gleixner
2023-05-22 14:19           ` Thomas Gleixner
2023-05-23 10:25             ` Marc Zyngier
2023-05-23 13:05               ` Thomas Gleixner
2023-05-31  8:35                 ` Marc Zyngier
2022-11-21 14:39 ` [patch V2 07/40] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count Thomas Gleixner
2022-11-21 14:39 ` [patch V2 08/40] genirq/irqdomain: Remove the param count restriction from select() Thomas Gleixner
2022-11-21 14:39 ` [patch V2 09/40] genirq/msi: Extend msi_parent_ops Thomas Gleixner
2022-11-21 14:39 ` [patch V2 10/40] irqchip: Provide irq-gic-lib Thomas Gleixner
2022-11-21 14:39 ` [patch V2 11/40] irqchip/gic-v3-its: Provide MSI parent infrastructure Thomas Gleixner
2022-11-21 14:39 ` [patch V2 12/40] irqchip/gic-msi-lib: Prepare for PCI MSI/MSIX Thomas Gleixner
2022-11-21 14:39 ` [patch V2 13/40] irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X] Thomas Gleixner
2022-11-21 14:39 ` [patch V2 14/40] genirq/irqdomain: Add BUS_DOMAIN_DEVICE_MSI Thomas Gleixner
2022-11-21 14:39 ` [patch V2 15/40] irqchip/gic-msi-lib: Prepare for DEVICE MSI to replace platform MSI Thomas Gleixner
2022-11-21 14:39 ` [patch V2 16/40] platform-msi: Prepare for real per device domains Thomas Gleixner
2022-11-21 14:39 ` [patch V2 17/40] irqchip: Convert all platform MSI users to the new API Thomas Gleixner
2022-11-21 14:39 ` [patch V2 18/40] genirq/msi: Provide optional translation op Thomas Gleixner
2022-11-21 14:39 ` [patch V2 19/40] genirq/msi: Split msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-21 14:39 ` [patch V2 20/40] genirq/msi: Provide BUS DEVICE_MSI_WIRED Thomas Gleixner
2022-11-21 14:39 ` [patch V2 21/40] genirq/msi: Optionally use dev->fwnode for device domain Thomas Gleixner
2022-11-21 14:39 ` [patch V2 22/40] genirq/msi: Provide allocation/free functions for "wired" MSI interrupts Thomas Gleixner
2022-11-21 14:39 ` [patch V2 23/40] genirq/irqdomain: Reroute device MSI create_mapping Thomas Gleixner
2022-11-21 14:39 ` [patch V2 24/40] irqchip/mbigen: Prepare for real per device MSI Thomas Gleixner
2022-11-21 14:39 ` [patch V2 25/40] irqchip/gic-msi-lib: Prepare for DOMAIN_BUS_WIRED_TO_MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 26/40] irqchip/gic-v3-its: Switch platform MSI to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 27/40] irqchip/mbigen: Remove platform_msi_create_device_domain() fallback Thomas Gleixner
2022-11-21 14:40 ` [patch V2 28/40] genirq/msi: Remove platform_msi_create_device_domain() Thomas Gleixner
2022-11-21 14:40 ` [patch V2 29/40] genirq/gic-v3-mbi: Remove unused wired MSI mechanics Thomas Gleixner
2022-11-21 14:40 ` [patch V2 30/40] genirq/gic-v3-mbi: Switch to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 31/40] irqchip/gic-v2m: Switch to device MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 32/40] genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV Thomas Gleixner
2022-11-21 14:40 ` [patch V2 33/40] irqchip/imx-mu-msi: Switch to MSI parent Thomas Gleixner
2022-11-28 20:47   ` Frank Li
2022-11-28 21:03     ` Thomas Gleixner
2022-11-21 14:40 ` [patch V2 34/40] irqchip/irq-mvebu-icu: Prepare for real per device MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 35/40] irqchip/mvebu-gicp: Switch to MSI parent Thomas Gleixner
2022-11-21 14:40 ` [patch V2 36/40] irqchip/mvebu-odmi: Switch to parent MSI Thomas Gleixner
2022-11-21 14:40 ` [patch V2 37/40] irqchip/irq-mvebu-sei: Switch to MSI parent Thomas Gleixner
2022-11-21 14:40 ` Thomas Gleixner [this message]
2022-11-21 14:40 ` [patch V2 39/40] genirq/msi: Remove platform MSI leftovers Thomas Gleixner
2022-11-21 14:40 ` [patch V2 40/40] genirq/msi: Move msi_device_data to core Thomas Gleixner
2023-01-11 19:29 ` [patch V2 00/40] genirq, irqchip: Convert ARM MSI handling to per device MSI domains Frank Li

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