From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Cai Huoqing <cai.huoqing@linux.dev>,
Robin Murphy <robin.murphy@arm.com>,
Jingoo Han <jingoohan1@gmail.com>, Frank Li <Frank.Li@nxp.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Serge Semin" <fancer.lancer@gmail.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
"Krzysztof Wilczyński" <kw@linux.com>,
caihuoqing <caihuoqing@baidu.com>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
linux-pci@vger.kernel.org, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v9 19/27] dmaengine: dw-edma: Use non-atomic io-64 methods
Date: Fri, 13 Jan 2023 20:14:01 +0300 [thread overview]
Message-ID: <20230113171409.30470-20-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20230113171409.30470-1-Sergey.Semin@baikalelectronics.ru>
Instead of splitting the 64-bits IOs up into two 32-bits ones it's
possible to use the already available non-atomic readq/writeq methods
implemented exactly for such cases. They are defined in the dedicated
header files io-64-nonatomic-lo-hi.h/io-64-nonatomic-hi-lo.h. So in case
if the 64-bits readq/writeq methods are unavailable on some platforms at
consideration, the corresponding drivers can have any of these headers
included and stop locally re-implementing the 64-bits IO accessors taking
into account the non-atomic nature of the included methods. Let's do that
in the DW eDMA driver too. Note by doing so we can discard the
CONFIG_64BIT config ifdefs from the code.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
---
drivers/dma/dw-edma/dw-edma-v0-core.c | 55 +++++++++------------------
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index 66f296daac5a..51a34b43434c 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -8,6 +8,8 @@
#include <linux/bitfield.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+
#include "dw-edma-core.h"
#include "dw-edma-v0-core.h"
#include "dw-edma-v0-regs.h"
@@ -53,8 +55,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
SET_32(dw, rd_##name, value); \
} while (0)
-#ifdef CONFIG_64BIT
-
#define SET_64(dw, name, value) \
writeq(value, &(__dw_regs(dw)->name))
@@ -80,8 +80,6 @@ static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
SET_64(dw, rd_##name, value); \
} while (0)
-#endif /* CONFIG_64BIT */
-
#define SET_COMPAT(dw, name, value) \
writel(value, &(__dw_regs(dw)->type.unroll.name))
@@ -164,14 +162,13 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
#define SET_LL_32(ll, value) \
writel(value, ll)
-#ifdef CONFIG_64BIT
-
static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
u64 value, void __iomem *addr)
{
+ unsigned long flags;
+
if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
u32 viewport_sel;
- unsigned long flags;
raw_spin_lock_irqsave(&dw->lock, flags);
@@ -181,22 +178,22 @@ static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
writel(viewport_sel,
&(__dw_regs(dw)->type.legacy.viewport_sel));
- writeq(value, addr);
+ }
+
+ writeq(value, addr);
+ if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)
raw_spin_unlock_irqrestore(&dw->lock, flags);
- } else {
- writeq(value, addr);
- }
}
static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
const void __iomem *addr)
{
- u32 value;
+ unsigned long flags;
+ u64 value;
if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
u32 viewport_sel;
- unsigned long flags;
raw_spin_lock_irqsave(&dw->lock, flags);
@@ -206,12 +203,12 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
writel(viewport_sel,
&(__dw_regs(dw)->type.legacy.viewport_sel));
- value = readq(addr);
+ }
+
+ value = readq(addr);
+ if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)
raw_spin_unlock_irqrestore(&dw->lock, flags);
- } else {
- value = readq(addr);
- }
return value;
}
@@ -225,8 +222,6 @@ static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
#define SET_LL_64(ll, value) \
writeq(value, ll)
-#endif /* CONFIG_64BIT */
-
/* eDMA management callbacks */
void dw_edma_v0_core_off(struct dw_edma *dw)
{
@@ -325,19 +320,10 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
/* Transfer size */
SET_LL_32(&lli[i].transfer_size, child->sz);
/* SAR */
- #ifdef CONFIG_64BIT
- SET_LL_64(&lli[i].sar.reg, child->sar);
- #else /* CONFIG_64BIT */
- SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar));
- SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar));
- #endif /* CONFIG_64BIT */
+ SET_LL_64(&lli[i].sar.reg, child->sar);
/* DAR */
- #ifdef CONFIG_64BIT
- SET_LL_64(&lli[i].dar.reg, child->dar);
- #else /* CONFIG_64BIT */
- SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar));
- SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar));
- #endif /* CONFIG_64BIT */
+ SET_LL_64(&lli[i].dar.reg, child->dar);
+
i++;
}
@@ -349,12 +335,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
/* Channel control */
SET_LL_32(&llp->control, control);
/* Linked list */
- #ifdef CONFIG_64BIT
- SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
- #else /* CONFIG_64BIT */
- SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr));
- SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr));
- #endif /* CONFIG_64BIT */
+ SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
}
void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
--
2.39.0
next prev parent reply other threads:[~2023-01-13 17:24 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 17:13 [PATCH v9 00/27] dmaengine: dw-edma: Add RP/EP local DMA controllers support Serge Semin
2023-01-13 17:13 ` [PATCH v9 01/27] dmaengine: Fix dma_slave_config.dst_addr description Serge Semin
2023-01-13 17:13 ` [PATCH v9 02/27] dmaengine: dw-edma: Release requested IRQs on failure Serge Semin
2023-01-13 17:13 ` [PATCH v9 03/27] dmaengine: dw-edma: Convert ll/dt phys-address to PCIe bus/DMA address Serge Semin
2023-01-13 17:13 ` [PATCH v9 04/27] dmaengine: dw-edma: Fix missing src/dst address of the interleaved xfers Serge Semin
2023-01-13 17:13 ` [PATCH v9 05/27] dmaengine: dw-edma: Don't permit non-inc " Serge Semin
2023-01-13 17:13 ` [PATCH v9 06/27] dmaengine: dw-edma: Fix invalid interleaved xfers semantics Serge Semin
2023-01-13 17:13 ` [PATCH v9 07/27] dmaengine: dw-edma: Add CPU to PCIe bus address translation Serge Semin
2023-01-13 17:13 ` [PATCH v9 08/27] dmaengine: dw-edma: Add PCIe bus address getter to the remote EP glue-driver Serge Semin
2023-01-20 23:29 ` Bjorn Helgaas
2023-01-21 20:37 ` Serge Semin
2023-01-13 17:13 ` [PATCH v9 09/27] dmaengine: dw-edma: Drop chancnt initialization Serge Semin
2023-01-20 23:54 ` Bjorn Helgaas
2023-01-21 21:10 ` Serge Semin
2023-01-13 17:13 ` [PATCH v9 10/27] dmaengine: dw-edma: Fix DebugFS reg entry type Serge Semin
2023-01-13 17:13 ` [PATCH v9 11/27] dmaengine: dw-edma: Stop checking debugfs_create_*() return value Serge Semin
2023-01-13 17:13 ` [PATCH v9 12/27] dmaengine: dw-edma: Add dw_edma prefix to the DebugFS nodes descriptor Serge Semin
2023-01-13 17:13 ` [PATCH v9 13/27] dmaengine: dw-edma: Convert DebugFS descs to being kz-allocated Serge Semin
2023-01-13 17:13 ` [PATCH v9 14/27] dmaengine: dw-edma: Rename DebugFS dentry variables to 'dent' Serge Semin
2023-01-13 17:13 ` [PATCH v9 15/27] dmaengine: dw-edma: Simplify the DebugFS context CSRs init procedure Serge Semin
2023-01-13 17:13 ` [PATCH v9 16/27] dmaengine: dw-edma: Move eDMA data pointer to DebugFS node descriptor Serge Semin
2023-01-13 17:13 ` [PATCH v9 17/27] dmaengine: dw-edma: Join Write/Read channels into a single device Serge Semin
2023-01-13 17:14 ` [PATCH v9 18/27] dmaengine: dw-edma: Use DMA-engine device DebugFS subdirectory Serge Semin
2023-01-13 17:14 ` Serge Semin [this message]
2023-01-21 0:54 ` [PATCH v9 19/27] dmaengine: dw-edma: Use non-atomic io-64 methods Bjorn Helgaas
2023-01-21 23:03 ` Serge Semin
2023-01-23 16:37 ` Bjorn Helgaas
2023-01-24 13:44 ` Serge Semin
2023-01-13 17:14 ` [PATCH v9 20/27] dmaengine: dw-edma: Drop DT-region allocation Serge Semin
2023-01-13 17:14 ` [PATCH v9 21/27] dmaengine: dw-edma: Replace chip ID number with device name Serge Semin
2023-01-13 17:14 ` [PATCH v9 22/27] dmaengine: dw-edma: Skip cleanup procedure if no private data found Serge Semin
2023-01-13 17:14 ` [PATCH v9 23/27] dmaengine: dw-edma: Add mem-mapped LL-entries support Serge Semin
2023-02-21 23:00 ` Bjorn Helgaas
2023-02-22 16:16 ` Vinod Koul
2023-01-13 17:14 ` [PATCH v9 24/27] dmaengine: dw-edma: Relax driver config settings Serge Semin
2023-01-20 22:50 ` Bjorn Helgaas
2023-01-22 0:11 ` Serge Semin
2023-01-23 16:43 ` Bjorn Helgaas
2023-01-24 14:49 ` Serge Semin
2023-01-24 23:47 ` Bjorn Helgaas
2023-01-25 14:40 ` Serge Semin
2023-01-25 23:23 ` Bjorn Helgaas
2023-01-26 16:37 ` Serge Semin
2023-01-26 18:19 ` Bjorn Helgaas
2023-01-26 21:16 ` Serge Semin
2023-01-13 17:14 ` [PATCH v9 25/27] PCI: dwc: Set coherent DMA-mask on MSI-address allocation Serge Semin
2023-01-20 21:59 ` Bjorn Helgaas
2023-01-22 0:34 ` Serge Semin
2023-01-13 17:14 ` [PATCH v9 26/27] PCI: bt1: Set 64-bit DMA-mask Serge Semin
2023-01-13 17:14 ` [PATCH v9 27/27] PCI: dwc: Add DW eDMA engine support Serge Semin
2023-01-13 18:34 ` [PATCH v9 00/27] dmaengine: dw-edma: Add RP/EP local DMA controllers support Serge Semin
2023-01-16 9:52 ` Lorenzo Pieralisi
2023-01-16 11:29 ` Serge Semin
2023-01-20 15:17 ` Lorenzo Pieralisi
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