From: Bjorn Helgaas <helgaas@kernel.org>
To: Lukas Wunner <lukas@wunner.de>
Cc: linux-pci@vger.kernel.org,
Gregory Price <gregory.price@memverge.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
"Li, Ming" <ming4.li@intel.com>, Hillf Danton <hdanton@sina.com>,
Ben Widawsky <bwidawsk@kernel.org>,
linuxarm@huawei.com, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 10/10] PCI/DOE: Relax restrictions on request and response size
Date: Mon, 23 Jan 2023 16:29:36 -0600 [thread overview]
Message-ID: <20230123222936.GA993507@bhelgaas> (raw)
In-Reply-To: <4dba01ff87d630abdd5a09d52e954d3c212d2018.1674468099.git.lukas@wunner.de>
Hi Lukas,
On Mon, Jan 23, 2023 at 11:20:00AM +0100, Lukas Wunner wrote:
> An upcoming user of DOE is CMA (Component Measurement and Authentication,
> PCIe r6.0 sec 6.31).
>
> It builds on SPDM (Security Protocol and Data Model):
> https://www.dmtf.org/dsp/DSP0274
>
> SPDM message sizes are not always a multiple of dwords. To transport
> them over DOE without using bounce buffers, allow sending requests and
> receiving responses whose final dword is only partially populated.
Can you add a note about this non-dwordness? The sec 6.30.1 Data
Object Header 2 "Length" field is in DW and the code in
pci_doe_send_req() and pci_doe_recv_resp() still reads/writes dwords.
I don't see the 6.31 text that requires non-dword sizes.
From a spec point of view, AFAICS, DOE is still specified in dwords,
but I guess you're leaving the actual PCI config-level DOE interface
in dwords and just making it more convenient for callers by having
pci_doe_*() hide the details of any partial dwords at the end by
transferring the entire dword over PCI but only copying the requested
bytes to/from the caller's buffer?
> Tested-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Lukas Wunner <lukas@wunner.de>
> Cc: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
> ---
> drivers/pci/doe.c | 66 ++++++++++++++++++++++++++++-------------------
> 1 file changed, 40 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
> index 0263bcfdddd8..2113ec95379f 100644
> --- a/drivers/pci/doe.c
> +++ b/drivers/pci/doe.c
> @@ -76,13 +76,6 @@ struct pci_doe_protocol {
> * @private: Private data for the consumer
> * @work: Used internally by the mailbox
> * @doe_mb: Used internally by the mailbox
> - *
> - * The payload sizes and rv are specified in bytes with the following
> - * restrictions concerning the protocol.
> - *
> - * 1) The request_pl_sz must be a multiple of double words (4 bytes)
> - * 2) The response_pl_sz must be >= a single double word (4 bytes)
> - * 3) rv is returned as bytes but it will be a multiple of double words
> */
> struct pci_doe_task {
> struct pci_doe_protocol prot;
> @@ -153,7 +146,7 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
> {
> struct pci_dev *pdev = doe_mb->pdev;
> int offset = doe_mb->cap_offset;
> - size_t length;
> + size_t length, remainder;
> u32 val;
> int i;
>
> @@ -171,7 +164,7 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
> return -EIO;
>
> /* Length is 2 DW of header + length of payload in DW */
> - length = 2 + task->request_pl_sz / sizeof(u32);
> + length = 2 + DIV_ROUND_UP(task->request_pl_sz, sizeof(u32));
> if (length > PCI_DOE_MAX_LENGTH)
> return -EIO;
> if (length == PCI_DOE_MAX_LENGTH)
> @@ -184,10 +177,20 @@ static int pci_doe_send_req(struct pci_doe_mb *doe_mb,
> pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
> FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH,
> length));
> +
> + /* Write payload */
> for (i = 0; i < task->request_pl_sz / sizeof(u32); i++)
> pci_write_config_dword(pdev, offset + PCI_DOE_WRITE,
> task->request_pl[i]);
>
> + /* Write last payload dword */
> + remainder = task->request_pl_sz % sizeof(u32);
> + if (remainder) {
> + val = 0;
> + memcpy(&val, &task->request_pl[i], remainder);
> + pci_write_config_dword(pdev, offset + PCI_DOE_WRITE, val);
> + }
> +
> pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_GO);
>
> return 0;
> @@ -207,11 +210,11 @@ static bool pci_doe_data_obj_ready(struct pci_doe_mb *doe_mb)
>
> static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
> {
> + size_t length, payload_length, remainder, received;
> struct pci_dev *pdev = doe_mb->pdev;
> int offset = doe_mb->cap_offset;
> - size_t length, payload_length;
> + int i = 0;
> u32 val;
> - int i;
>
> /* Read the first dword to get the protocol */
> pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
> @@ -238,15 +241,34 @@ static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *tas
>
> /* First 2 dwords have already been read */
> length -= 2;
> - payload_length = min(length, task->response_pl_sz / sizeof(u32));
> - /* Read the rest of the response payload */
> - for (i = 0; i < payload_length; i++) {
> - pci_read_config_dword(pdev, offset + PCI_DOE_READ,
> - &task->response_pl[i]);
> + received = task->response_pl_sz;
> + payload_length = DIV_ROUND_UP(task->response_pl_sz, sizeof(u32));
> + remainder = task->response_pl_sz % sizeof(u32);
> + if (!remainder)
> + remainder = sizeof(u32);
> +
> + if (length < payload_length) {
> + received = length * sizeof(u32);
> + payload_length = length;
> + remainder = sizeof(u32);
> + }
> +
> + if (payload_length) {
> + /* Read all payload dwords except the last */
> + for (; i < payload_length - 1; i++) {
> + pci_read_config_dword(pdev, offset + PCI_DOE_READ,
> + &task->response_pl[i]);
> + pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
> + }
> +
> + /* Read last payload dword */
> + pci_read_config_dword(pdev, offset + PCI_DOE_READ, &val);
> + memcpy(&task->response_pl[i], &val, remainder);
> /* Prior to the last ack, ensure Data Object Ready */
> - if (i == (payload_length - 1) && !pci_doe_data_obj_ready(doe_mb))
> + if (!pci_doe_data_obj_ready(doe_mb))
> return -EIO;
> pci_write_config_dword(pdev, offset + PCI_DOE_READ, 0);
> + i++;
> }
>
> /* Flush excess length */
> @@ -260,7 +282,7 @@ static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *tas
> if (FIELD_GET(PCI_DOE_STATUS_ERROR, val))
> return -EIO;
>
> - return min(length, task->response_pl_sz / sizeof(u32)) * sizeof(u32);
> + return received;
> }
>
> static void signal_task_complete(struct pci_doe_task *task, int rv)
> @@ -560,14 +582,6 @@ static int pci_doe_submit_task(struct pci_doe_mb *doe_mb,
> if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type))
> return -EINVAL;
>
> - /*
> - * DOE requests must be a whole number of DW and the response needs to
> - * be big enough for at least 1 DW
> - */
> - if (task->request_pl_sz % sizeof(u32) ||
> - task->response_pl_sz < sizeof(u32))
> - return -EINVAL;
> -
> if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
> return -EIO;
>
> --
> 2.39.1
>
next prev parent reply other threads:[~2023-01-23 22:29 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-23 10:10 [PATCH v2 00/10] Collection of DOE material Lukas Wunner
2023-01-23 10:11 ` [PATCH v2 01/10] PCI/DOE: Silence WARN splat with CONFIG_DEBUG_OBJECTS=y Lukas Wunner
2023-01-24 0:33 ` Ira Weiny
2023-01-24 10:32 ` Jonathan Cameron
2023-01-25 21:05 ` Lukas Wunner
2023-01-24 16:18 ` Gregory Price
2023-02-10 23:50 ` Dan Williams
2023-01-23 10:12 ` [PATCH v2 02/10] PCI/DOE: Fix memory leak " Lukas Wunner
2023-01-24 0:35 ` Ira Weiny
2023-01-24 10:33 ` Jonathan Cameron
2023-02-10 23:52 ` Dan Williams
2023-01-23 10:13 ` [PATCH v2 03/10] PCI/DOE: Provide synchronous API and use it internally Lukas Wunner
2023-01-24 0:48 ` Ira Weiny
2023-01-24 10:40 ` Jonathan Cameron
2023-01-24 20:07 ` Ira Weiny
2023-02-10 23:57 ` Dan Williams
2023-01-23 10:14 ` [PATCH v2 04/10] cxl/pci: Use synchronous API for DOE Lukas Wunner
2023-01-24 0:52 ` Ira Weiny
2023-02-03 8:53 ` Li, Ming
2023-02-03 8:56 ` Li, Ming
2023-02-03 9:54 ` Lukas Wunner
2023-01-24 11:01 ` Jonathan Cameron
2023-02-10 22:17 ` Lukas Wunner
2023-01-23 10:15 ` [PATCH v2 05/10] PCI/DOE: Make asynchronous API private Lukas Wunner
2023-01-24 0:55 ` Ira Weiny
2023-01-24 11:03 ` Jonathan Cameron
2023-01-23 10:16 ` [PATCH v2 06/10] PCI/DOE: Allow mailbox creation without devres management Lukas Wunner
2023-01-24 12:15 ` Jonathan Cameron
2023-01-24 12:18 ` Jonathan Cameron
2023-02-03 9:06 ` Li, Ming
2023-02-03 9:09 ` Li, Ming
2023-02-03 10:08 ` Lukas Wunner
2023-02-10 22:03 ` Lukas Wunner
2023-01-23 10:17 ` [PATCH v2 07/10] PCI/DOE: Create mailboxes on device enumeration Lukas Wunner
2023-01-24 1:14 ` Ira Weiny
2023-01-24 12:21 ` Jonathan Cameron
2023-01-23 10:18 ` [PATCH v2 08/10] cxl/pci: Use CDAT DOE mailbox created by PCI core Lukas Wunner
2023-01-24 1:18 ` Ira Weiny
2023-01-24 12:25 ` Jonathan Cameron
2023-01-23 10:19 ` [PATCH v2 09/10] PCI/DOE: Make mailbox creation API private Lukas Wunner
2023-01-24 1:25 ` Ira Weiny
2023-01-24 12:26 ` Jonathan Cameron
2023-01-23 10:20 ` [PATCH v2 10/10] PCI/DOE: Relax restrictions on request and response size Lukas Wunner
2023-01-23 22:29 ` Bjorn Helgaas [this message]
2023-01-24 1:43 ` Ira Weiny
2023-02-10 21:47 ` Lukas Wunner
2023-01-24 12:43 ` Jonathan Cameron
2023-01-24 23:51 ` Bjorn Helgaas
2023-01-25 9:47 ` Jonathan Cameron
2023-02-10 22:10 ` Lukas Wunner
2023-01-23 22:30 ` [PATCH v2 00/10] Collection of DOE material Bjorn Helgaas
2023-02-10 21:39 ` Lukas Wunner
2023-02-11 0:04 ` Dan Williams
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