From: Abel Vesa <abel.vesa@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-phy@lists.infradead.org,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: [PATCH v5 12/12] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes
Date: Tue, 24 Jan 2023 14:47:14 +0200 [thread overview]
Message-ID: <20230124124714.3087948-13-abel.vesa@linaro.org> (raw)
In-Reply-To: <20230124124714.3087948-1-abel.vesa@linaro.org>
Enable PCIe controllers and PHYs nodes on SM8550 MTP board.
Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
This patch does not have a v3, but since it is now part of the same
patchset with the controller and the phy drivers patches, I had to
bump the version to 4.
The v4 was here:
https://lore.kernel.org/all/20230118230526.1499328-3-abel.vesa@linaro.org/
Changes since v4:
* moved here the pinctrl properties and out of dtsi file
Changes since v2:
* none
Changes since v1:
* ordered pcie related nodes alphabetically in MTP dts
* dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes
* dropped the child node from the phy nodes, like Johan suggested,
and updated to use the sc8280xp binding scheme
* changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy
to "nocsr"
* reordered all pcie nodes properties to look similar to the ones
from sc8280xp
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 37 +++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 81fcbdc6bdc4..31e039f10a1b 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -359,6 +359,43 @@ vreg_l3g_1p2: ldo3 {
};
};
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p91>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
--
2.34.1
prev parent reply other threads:[~2023-01-24 12:49 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 12:47 [PATCH v5 00/12] sm8550: Add PCIe HC and PHY support Abel Vesa
2023-01-24 12:47 ` [PATCH v5 01/12] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa
2023-01-26 11:03 ` Krzysztof Kozlowski
2023-01-24 12:47 ` [PATCH v5 02/12] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa
2023-01-24 12:47 ` [PATCH v5 03/12] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 04/12] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 05/12] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 06/12] phy: qcom-qmp: qserdes-txrx: " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 07/12] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 08/12] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa
2023-01-24 12:47 ` [PATCH v5 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
2023-01-26 11:05 ` Krzysztof Kozlowski
2023-01-24 12:47 ` [PATCH v5 10/12] PCI: qcom: Add SM8550 PCIe support Abel Vesa
2023-01-24 12:47 ` [PATCH v5 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes Abel Vesa
2023-01-24 12:47 ` Abel Vesa [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230124124714.3087948-13-abel.vesa@linaro.org \
--to=abel.vesa@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=kishon@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mani@kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=p.zabel@pengutronix.de \
--cc=robh@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).