From: Abel Vesa <abel.vesa@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Johan Hovold" <johan+linaro@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: [PATCH v9 07/11] phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
Date: Wed, 8 Feb 2023 20:00:16 +0200 [thread overview]
Message-ID: <20230208180020.2761766-8-abel.vesa@linaro.org> (raw)
In-Reply-To: <20230208180020.2761766-1-abel.vesa@linaro.org>
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
The v8 of this patch is:
https://lore.kernel.org/all/20230206212619.3218741-8-abel.vesa@linaro.org/
Changes since v8:
* none
Changes since v7:
* none
Changes since v6:
* none
Changes since v5:
* none
Changes since v4:
* none
Changes since v3:
* none
Changes since v2:
* none
Changes since v1:
* split all the offsets into separate patches, like Vinod suggested
.../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 +++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 1 +
2 files changed, 33 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
new file mode 100644
index 000000000000..86d7d796d5d7
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
+#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
+
+#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
+#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
+#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
+#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
+#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
+#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index e5974e6caf51..148663ee713a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -24,6 +24,7 @@
#include "phy-qcom-qmp-qserdes-com-v6.h"
#include "phy-qcom-qmp-qserdes-txrx-v6.h"
#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
+#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
#include "phy-qcom-qmp-qserdes-pll.h"
--
2.34.1
next prev parent reply other threads:[~2023-02-08 18:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-08 18:00 [PATCH v9 00/11] sm8550: Add PCIe HC and PHY support Abel Vesa
2023-02-08 18:00 ` [PATCH v9 01/11] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa
2023-02-08 18:00 ` [PATCH v9 02/11] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa
2023-02-08 18:00 ` [PATCH v9 03/11] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa
2023-02-08 18:00 ` [PATCH v9 04/11] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa
2023-02-08 18:00 ` [PATCH v9 05/11] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa
2023-02-08 18:00 ` [PATCH v9 06/11] phy: qcom-qmp: qserdes-txrx: " Abel Vesa
2023-02-08 18:00 ` Abel Vesa [this message]
2023-02-08 18:00 ` [PATCH v9 08/11] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa
2023-02-08 18:00 ` [PATCH v9 09/11] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
2023-02-08 18:00 ` [PATCH v9 10/11] PCI: qcom: Add SM8550 PCIe support Abel Vesa
2023-02-08 18:00 ` [PATCH v9 11/11] arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes Abel Vesa
2023-02-10 16:58 ` [PATCH v9 00/11] sm8550: Add PCIe HC and PHY support Vinod Koul
2023-03-15 23:34 ` (subset) " Bjorn Andersson
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